PCB design
High-speed, RF, high-current, thermal-critical boards. We design the board the way we’d design our own.
- 1–99 layer stackups
- DDR4/5, PCIe, 100G SerDes
- RF up to mmWave
- Rigid-flex, chip-on-board
⌁ Engineering, not drafting
PCBs that
PCBs that
obey physics.
Senior EEs design your board against real signal, power, and thermal physics — and we ship you the TRM thermal report to prove it.
- 300+ designs
- 20+ years
- 1–99 layers
- Altium · Orcad · Siemens
U7
81 °C @ 2.4 A
+12 thermal vias → 69 °C
40 °C
100 °C
Trusted by hardware teams shipping
DDR5 @ 6400 MT/s
PCIe Gen 5
100G SerDes
0.1–28 GHz RF
200 A rails
Rigid-flex
⌁ New · The Lab
Enter Lab →
Where physics, silicon, and AI converge.
Experiments, puzzles, and ideas that don’t fit on the main site. Drag a trace through a 0.5 mm-pitch BGA. Solve the breakout.
Three things. Done at physics-grade.
TRM thermal simulation
Steady-state and transient PCB thermal + PDN, browser-trial, credit-card pricing, Altium-integrated. Co-developed with Adam Research.
- 1–99 layers, SMD + TH + embedded
- Current density, voltage drop, T(°C)
- Pre- and post-layout
- 14-day trial · no sales call
AI tools, free
Free calculators and AI copilots that the PCB industry hasn’t built. Use them anonymously, no signup.
- Φ Gerber — AI Gerber review
- Φ Stack — stackup sage
- Φ DFM — translator
- Φ Datasheet — Q&A on any PDF
⌁ Live demo · no signup
Drop a Gerber. Get an AI review in 30 seconds.
Φ Gerber inspects your stack, traces, vias, and copper pour against IPC-2152 and 20 years of PhyCircuit field experience. You get a plain-English report and a list of fixes you can paste into Altium.
- ✓ DRC violations explained like a senior engineer would
- ✓ Thermal hotspots predicted before fab
- ✓ Stackup sanity check vs. impedance targets
- ✓ Cited against IPC-2152 / 2221 / 7351
The thermal sim engineers actually use.
1–99 layers. Steady-state and transient. Pre- and post-layout. Altium-integrated. Browser trial. Credit-card priced.
Start free 14-day trial →99
layers max
±3 °C
typical vs. lab measurement
5 min
first sim, no meshing
1/10×
price of Icepak
Boards we signed off this quarter.
Anonymized at client request. Stats are real.
14-layer DDR5 server
- 14 layers
- DDR5 @ 6400 MT/s
- 28 diff pairs
- ±3 ps skew
Re-spun a vendor design that wouldn’t train above 4800. Stackup change, escape re-route, and a TRM thermal report that ended the procurement debate.
Read the case study →120 A buck supply, EV
- 6 layers
- 120 A continuous
- 3 oz copper
- 82 °C max
Customer wanted to know if 2 oz copper plus heatsinks would be enough. TRM said no — we re-spec’d to 3 oz and saved a re-spin in NPI.
Read the case study →5.8 GHz RF transceiver
- 8 layers
- Rogers 4350B
- −110 dBm noise floor
- 50 Ω ± 5 %
Mixed-signal board with 5.8 GHz RF on the same stackup as a Cortex-M and a buck supply. We isolated, shielded, and proved the RF NF in measurement.
Read the case study →
⌁ Field guide · free PDF
The PCB Designer’s Field Guide
40 pages of checklists for high-speed, RF, thermal, and manufacturing. Written by our senior EEs. No LLMs.
Ready when you are.
Senior EEs answer every inbound. No SDR funnel. No 9-step discovery call.