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Power density > 5 W/cm²
Once average power density crosses 5 W/cm², “looks fine” stops being a strategy. Sign-off is cheaper than a re-spin.
Thermal sign-off, by physicists.
A category we own. Every PhySignoff engagement ships with a full TRM thermal report, PDN verification, and an IPC class verdict your VP of Engineering can put their signature on.
⌁ Named deliverable
What you actually receive.
Not a slide deck. A 30–60 page engineering report with every plot you’d run yourself if you had a year and TRM, plus the design fixes already applied to the board.
- 01Stackup & impedance sheetPer-layer dielectric, copper, and Z-target.
- 02Per-component thermal tableTj, Tc, Tboard at expected ambient + worst-case.
- 033D thermographic plotSteady-state heatmap, every layer, every face.
- 04Transient sweepPower-cycle and inrush time-response per net.
- 05Current density & voltage dropA/mm² and mΩ resolution, layer-by-layer.
- 06IPC class verdictClass 2 / 3 / 3A pass/fail with rationale.
- 07Reliability statementMTBF estimate with Arrhenius derate.
- 08Recommended fixesApplied to the board AND listed as a delta vs. baseline.
If any of these are true.
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Mission-critical (IPC 3 / 3A)
Aerospace, defense, medical, automotive ISO 26262 — the cert auditor will ask for the report. We hand it over.
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Field returns
Boards coming back from the field with thermal failures? We forensically rebuild the cause and prove the fix.
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NPI gating
VP of Engineering needs a stamp before fab release. We sign off externally — no internal politics.
14-layer DDR5 server, re-spun without melt-down.
The brief
A Series-B silicon startup brought us a 14-layer board that wouldn’t train DDR5 above 4800 MT/s. Their thermal margin was a guess. Their VP of Engineering needed a signature before NPI.
What we found
- Stackup mistuned by 7 mil — Z0 drifted to 47 Ω against a 50 Ω target.
- BGA escape route created a hidden thermal choke under U7 (DDR PHY).
- VRM placement put the inductor 6 mm from the regulator — copper too thin to carry 2.4 A continuous.
What we delivered
- Re-spun stackup with TRM-correlated impedance plan.
- BGA escape redesigned + 12 thermal vias under the DDR PHY.
- VRM relocated 2 mm closer + copper widened 60 %.
- 40-page TRM sign-off report. Class 2 with 7 °C margin.
Outcome
Board trained at full 6400 MT/s on first article. Thermal max measured at 79 °C against 82 °C predicted (≤ 4 % error). Customer signed off on NPI 11 days later.
Get a signed-off board.
Senior EEs answer every inbound. The RFQ scoper gives you a fixed-fee band in 60 seconds.