PCB impedance calculator.
Real-time microstrip, stripline, and edge-coupled differential. Numbers match Polar SI9000 within 1–3% across typical PCB geometries.
Approximations valid for 0.5 ≤ w/h ≤ 10, εᵣ 2–10. Results within 1–3% of Polar SI9000 in this range. For controlled-impedance fab, confirm with your fab’s stackup engineer.
How this works
This calculator implements the IPC-2141 / Hammerstad & Jensen closed-form approximations for surface microstrip and offset stripline, plus the standard k-coupling correction for edge-coupled differential pairs.
Microstrip (signal on top, plane underneath)
Used when the trace is on the outer layer of a board and the next layer down is a solid plane. Air on top means the effective dielectric is lower than εr — usually around 3.0–3.4 for FR-4.
w/h ≤ 1: Z₀ = (60/√εeff) · ln(8h/w + w/(4h))
w/h ≥ 1: Z₀ = (120π/√εeff) / (w/h + 1.393 + 0.667·ln(w/h + 1.444))Stripline (signal sandwiched between two planes)
Used on inner layers where the trace has a plane above and below. Effective ε is the full εr. Better signal integrity, but uses an extra layer.
b = h₁ + h₂ + t
Z₀ = (60/√εr) · ln(4b / (0.67π·(0.8w + t)))Differential pairs
Two coupled lines with spacing s. The differential impedance is approximately 2·Zodd. Odd-mode impedance Zodd drops as s shrinks because of mutual coupling. We compute the coupling coefficient k and apply IPC-2141 differential correction.
What this does NOT do
- Frequency-dependent dielectric loss (use Polar Si9000 or full-wave HFSS for fast SerDes).
- Roughness modeling (Huray, Cannonball). Below 5 GHz the impedance shift is < 1%.
- Plating / etch correction (assume rectangular cross-section).
Used by PhyCircuit
This same calculator (with frequency-domain extensions) runs inside every PhyCircuit design engagement. See services or scope a project if you want us to design the board the impedance is going on.