Thermal via array.

Estimate the conduction thermal resistance of a via array under an exposed pad. See why — past ~12 vias — more copper area beats more vias.

⌁ Via-array thermal resistance

—

°C/W

ΔT across vias—

Cu area / via—

Total Cu area—

This models only the conduction resistance through the via barrels — the easy part. The dominant resistance is usually the copper plane spreading underneath and the convection to ambient. That’s why adding vias past ~12 barely helps: you’re optimizing the wrong resistor. The full picture needs a 3D sim — TRM does this. See the thermal via design guide.

How it’s computed

Each via barrel is a copper cylinder conducting heat from the exposed pad down to the inner/bottom plane. Its thermal resistance is:

θ_via = L / (k · A_cu)

  L     = board thickness pad→plane (m)
  k     = 385 W/m·K (copper)
  A_cu  = copper cross-sectional area of one via (m²)

For a plated (hollow) via, the copper is an annulus of plating thickness t:

A_cu = π · ( r_outer² − (r_outer − t)² )   where r_outer = hole_d / 2

For a copper-filled via, the full bore conducts: A_cu = π · r_outer².

N vias act as resistors in parallel:

θ_array = θ_via / N
ΔT = θ_array · Power

Why “more vias” hits a wall

θ_array drops as 1/N — so going 4 → 8 vias halves it, but 24 → 36 barely moves it because the array resistance is already small compared to the spreading resistance of the copper plane it dumps into. Past ~12 vias on a typical 5×5 mm pad, your engineering effort is better spent enlarging the layer-2 copper. We measured this; the writeup is in Proximity over Quantity.

What this ignores (and TRM doesn’t)

Plane spreading resistance (usually dominant above ~2 W).
Convection + radiation to ambient.
Solder void fraction under the pad (can add 20–40%).
Interaction with neighboring hot components.

For a board where thermal margin matters, PhySignoff delivers a full TRM report with measured correlation.