BGA escape routing is the first thing that breaks when a board gets dense. Every signal pin buried inside a 0.5 mm-pitch BGA grid must exit to a via — and the geometry is brutal: at 0.5 mm pitch there are only three routing channels between pad rows, each wide enough for a single 0.1 mm trace. This puzzle puts you in that constraint. Route every signal out. Don’t cross yourself. Don’t run out of channels.
Tip: plan the inner-ring pins first — they have the fewest exit channels and constrain everything else, exactly like real BGA fanout design.
At 0.5 mm BGA pitch, IPC-2226 Class B rules allow a 0.25 mm pad, a 0.1 mm trace, and a 0.1 mm clearance. That geometry leaves exactly three routing channels between adjacent pad rows — one per gap. Miss that and you cannot escape the pin without a buried or microvia.
Scale up to 800+ pins (think Xilinx UltraScale, Apple M-series, or any modern SoC) and you run out of outer-layer channels completely. That forces a via-in-pad or microvia stackup, adds two to four PCB layers, and can double board cost. The puzzle compresses that reality into a solvable grid — same logic, same trade-offs.
See the full engineering breakdown in the BGA escape routing guide →
score = max(0, base − length·5 − vias·50 + bonus·2)
Base 1000 per level. Trace length penalty (5 per cell) rewards short routes. Via penalty (50 per via) rewards single-layer solves. Time bonus (2 per second remaining vs target) rewards quick solves. Stars: 3 ≥ 85%, 2 ≥ 65%, 1 = pass.
Grid cell spacing mirrors 0.5 mm BGA pitch. Each channel gap fits one trace — matching IPC-2226 Class B geometry (0.1 mm trace / 0.1 mm clearance on a 0.25 mm pad). Via penalty (50 pts) approximates the real cost: each via eats a routing channel and adds drill cost. Three-star solves require the same fanout discipline a senior layout engineer uses. Read the full BGA escape guide →