The DDR5 server that wouldn’t train.
- 14 layers
- DDR5 6400 MT/s
- 28 diff pairs
- ±3 ps skew
ProblemA Series-B silicon startup’s vendor board topped out at DDR5-4800 and no one knew why. NPI was blocked on a thermal + SI sign-off.
What we foundStackup mistuned by 7 mil (Z₀ at 47 Ω vs. 50 Ω target); a BGA escape that added a via stub on the strobe; a hidden thermal choke under the DDR PHY.
What we didRe-tuned the stackup, back-drilled the offending vias, re-matched at the escape, added 12 thermal vias under U7, and shipped a full TRM thermal report.