Thermal via design rules.
Why placement beats quantity in QFN thermal management. With TRM cross-sections of 9 different via arrays and one surprising counter-intuitive result.
Read the guide ↗How we’d train a junior EE.
Pillar guides, deep-dive articles with real TRM data, formal publications, and a free 40-page field guide. No LLM slop. No filler.
One new piece a week.
Thermal
Proximity over quantity: QFN thermal vias
Counter-intuitive result — copper plane placement beats via count for QFNs above 2 W.
SignalDDR4 routing — the only rules that matter
30 % of the published DDR4 rules don’t affect signal integrity. Here are the 12 that do.
PDNPDN target impedance from scratch
Derive your target Z(f) from the datasheet. With a worked example you can follow line by line.
ThermalQFN thermal pad design — what moves Tj
Paste voids, via arrays, and the geometry that actually lowers junction temperature.
CompareTRM vs Icepak — honest comparison
Board thermal vs enclosure CFD. What each tool is for, where each wins, where TRM loses.
StandardsIPC class 2 vs class 3 — when does it matter?
The class verdict isn’t just an audit checkbox — it changes your stackup, your via specs, your hi-pot.
SignalDifferential pair matching — how tight?
Intra-pair vs inter-pair skew, the budget math, and fixing it at the bend, not downstream.
SignalPCIe Gen 5 layout — keep the eye open
At 32 GT/s it’s a loss budget: backdrilling, low-loss material, reference continuity.
PDNDecoupling — beyond “0.1 µF everywhere”
Self-resonance, anti-resonance, and why mounting inductance beats the cap value.
FlexRigid-flex — bend rules that don’t crack
Bend radius, bookbinder construction, and the rigid-to-flex transition that fails first.
ThermalBeyond vias: coins, inlays, heat pipes
The cooling escalation ladder for extreme power density — and when each rung is worth it.
Signal + PowerUSB-C & Power Delivery layout
High-current VBUS and 20 Gbps SuperSpeed on one connector — plus the CC/mux/ESD details that pass compliance.
CompareTRM vs HyperLynx Thermal
A senior EE’s take on board-level thermal + PDN: where each tool wins, and when a HyperLynx shop should add TRM.
CompareTRM vs SolidWorks Flow
They solve different problems — coupled electrical-thermal vs CFD. When you need each, and when the right answer is both.
CompareKiCad vs Altium for high-speed
Where KiCad now suffices, where Altium still wins for DDR5/PCIe Gen5/100G — a verdict by project class, not by reflex.
Stackup4 vs 6 vs 8 layer — how to pick
The cost curve, when plane integrity forces a bump, the BGA escape gate, and a 5-step rubric that survives most projects.
PillarStackup design — the rules of plane integrity
The thing that makes a stackup work isn’t the layer count — it’s plane integrity. Five non-negotiables, a worked DDR4 example, and a short rubric.
PillarPCB DFM gotchas — the 12 fab-killers
The twelve fab-house findings that account for ~80% of real re-spins. Yield killers, reliability killers, process killers — each with a number you can hit in CAD.
PillarBGA escape routing — the patterns that survive
The escape IS the design. Pitch-by-pitch decisions, four canonical patterns, when via-in-pad is required, and the SI gotchas at the breakout.
PillarEMC for power supplies — layouts that pass first-time
The four loops that radiate, the filter design rules, and a ten-item layout checklist that turns the chamber visit into a verification, not a hunt.
Our DesignCon-grade work.
Available as PDF + on-page HTML so the content is actually indexable. Submit your own peer-review request →
2025-08
Proximity Over Quantity
How copper plane placement outperforms thermal via count in QFN package thermal management. Methodology, TRM correlation, and a 12 % thermal margin lift.
Read · Download PDF ↗ 2025-08A Study on EVAL-LTM4703-AZ with TRM
Thermal analysis of the LTM4703 evaluation board using TRM. Bench measurement vs simulation, with the 1.8 °C delta explained.
Read · Download PDF ↗
⌁ Field guide · free PDF
The PCB Designer’s Field Guide.
40 pages of checklists for high-speed, RF, thermal, and manufacturing. Written by our senior EEs. No LLMs.
One design rule a week.
Newsletter: one rule, one figure, one mistake we’ve seen this week. ~ 4 min read. Unsubscribe in one click.