The PCB Designer’s Field Guide.
The checklists our senior EEs actually use, distilled from 300+ board sign-offs — high-speed, RF, power, thermal, and manufacturing. No email wall to read it; print it or save as PDF with one click.
High-speed digital
The rules that decide whether a fast bus trains on the first article.
- Set the stackup before routing a single net. Confirm controlled-impedance targets (50 Ω SE / 100 Ω diff, 40 Ω DDR) against your fab’s real process — not the default. Calculate it.
- Continuous reference under every fast trace. No plane splits, no crossing a gap. A split under a byte lane is the #1 DDR failure we re-spin.
- Return via within ~40 mil of every layer transition. The signal’s return current has to follow it.
- Match intra-pair tight (≤ ~1 ps), inter-pair loose. Fix skew at the bend/breakout, not with a downstream serpentine. How.
- Backdrill / blind-via the stubs at Gen5 / 25G+. Via stubs resonate in-band and notch the channel. PCIe Gen5.
- Past a few inches at multi-GHz it’s a loss budget — pick a low-loss laminate + low-profile copper.
RF & microwave
Where the noise budget is won or lost.
- Hybrid stack beats all-Rogers below ~10 GHz. Put the RF layer on low-loss material; keep the rest FR-4.
- Match the feed and the launch. EM-simulate the connector launch and antenna feed; via-fence the transmission lines.
- Isolate aggressively. Guard rings, stitching, a quiet reference island, and keep the switcher return away from the LNA reference.
- Hatch the reference under flexing RF. Solid copper stiffens and cracks flex; hatch it (accept the impedance trade).
Power & thermal
Above ~2 W per package, “looks fine” stops being a strategy.
- Size copper for current with margin. IPC-2221 is conservative; IPC-2152 is realistic. Calculate it, then validate hot rails in TRM.
- Proximity over quantity on thermal vias. Get ~9–12 good vias, then enlarge the layer-2 copper — don’t chase via #20. Why.
- Windowpane the QFN paste. A segmented aperture (60–80%) keeps solder voids under ~15% — worth real °C. How.
- Climb the cooling ladder one rung at a time: vias → heavy copper → copper coin → IMS → embedded heat pipe. Earn each rung with a TRM number. Ladder.
- Derate for ambient. 85 °C and 125 °C eat your margin fast; sim at worst-case + 15 °C.
Power integrity (PDN)
Quiet rails come from an impedance target, not a copy-pasted decap list.
- Derive the target impedance first: Z = (V·ripple%)/ΔI. Every decap decision flows from it. Worked example.
- Tile capacitor SRFs across the band; keep values within ~a decade to avoid deep anti-resonance peaks. How.
- Smallest, lowest-ESL caps at the power balls; via-in-pad for BGAs. Mounting inductance beats cap value at HF.
- Check DC IR-drop at the far-end load — on a 0.9 V rail you have ~45 mV to spend. Calculate it.
- Never split a plane under a fast signal. Tight power/ground plane pair = free HF capacitance.
Manufacturing & sign-off
The boring checklist that prevents the expensive re-spin.
- Decide your IPC class before stackup + via planning. Class 3 (no annular-ring breakout, 25 µm plating) changes your design, not just inspection. Which class?
- Run the fab’s DFM and actually read it. Annular ring, drill-to-copper, soldermask slivers, acid traps. Translate a report.
- Include every layer in the fab pack — outline/keepout, drill, mask, paste. A missing outline is fab-stopping. Check your Gerbers.
- Match assembly class to board class (IPC-A-610 to IPC-6012) — a class-3 board with class-2 assembly is a costly mismatch.
- Thermal sign-off before release if power density > 5 W/cm² or the spec says IPC 3. PhySignoff.
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