Adjust the dielectric height h until every trace on the board hits its Z0 target. Five levels, from a single 50 Ω microstrip to a three-target DDR5 challenge. The same Hammerstad/Wheeler math that runs in the impedance calculator runs here in real time.
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| Trace | Target | Computed Z0 | Status |
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Each impedance value is computed using the same closed-form Hammerstad/Wheeler approximation as the impedance calculator. For microstrip: Z0 = f(w, h, t, εr). Adjust h and Z0 changes in real time. There’s always exactly one h that satisfies the targets — finding it is the puzzle.
In a real stackup, h is the prepreg/core thickness between the signal trace and its reference plane. Thicker dielectric → lower coupling → higher Z0. Thinner → lower Z0. Fabs control h to a specific tolerance (±10% standard, ±5% with named material) so getting the right h is an actual engineering problem.
On a real PCB, every trace on the same layer shares the same h. If you need 50 Ω single-ended AND 100 Ω differential on the same layer, the trace widths must be chosen so both targets are satisfied at the same h. Level 5 is a real DDR5 scenario — three widths, one h.
Φ Stack builder auto-solves for the geometry that hits your targets — three AI-suggested alternatives on one click.