PCIe Gen 5 layout — the rules that keep the eye open.
TL;DR
- Gen 5 runs 32 GT/s — at that rate the board is a loss budget, not a length-matching exercise. Insertion loss, via stubs, and reference continuity decide whether the link trains.
- Backdrill the via stubs and pick a low-loss laminate (Megtron 6 class) past trivial trace lengths. FR-4 runs out of margin fast at 16 GHz Nyquist.
- Keep an unbroken reference plane and place AC-coupling caps cleanly — a sloppy cap pad is a bigger impedance discontinuity than people expect.
At 32 GT/s, it’s a loss budget
Gen 5’s Nyquist is 16 GHz. Channel insertion loss, not propagation delay, is the gating constraint — the spec allocates a finite dB budget from package to package, and every trace inch, via, connector, and AC cap spends some of it. Your job is to stay inside that budget so the receiver’s CTLE/DFE equalization can still recover the eye. That reframes layout: minimize loss and discontinuities, and stop obsessing over absolute length.
The rules that matter
- Material. FR-4’s Df eats the budget by ~a few inches at Gen 5. Use a low-loss laminate (Megtron 6, Tachyon, or similar) for the SerDes layers — often a hybrid stack to control cost.
- Reference continuity. Route each lane over one continuous ground reference. No plane splits, no crossing a gap — that’s a guaranteed reflection and mode conversion.
- Smooth copper. Conductor roughness adds loss at 16 GHz; spec a low-profile (VLP/HVLP) copper foil.
- AC-coupling caps. Use small body sizes (0201/0402), optimize the pad/anti-pad to minimize the capacitive discontinuity, and keep the reference tight under the cap.
- Connector launch. Tune the breakout and the connector footprint anti-pads; this is where a surprising fraction of return loss lives.
Vias & backdrilling
A through-via to an inner layer leaves a stub below the exit layer. At Gen 5 that stub resonates inside the band and notches the channel — it’s the single most common reason a Gen 5 link won’t train. Backdrill the stubs (remove the unused barrel), or use blind/buried vias. Keep the remaining stub well under ~10 mil. Co-locate and symmetrize the P/N via transitions.
Gen 4 forgives. Gen 5 doesn’t. Treat every via stub and reference gap as loss you can’t get back.
PCIe Gen 5 checklist
- ☐ Low-loss laminate on SerDes layers (hybrid stack OK)
- ☐ Low-profile copper foil specified
- ☐ Backdrill (or blind/buried) all signal vias; residual stub < 10 mil
- ☐ Continuous ground reference, no splits, return vias at every transition
- ☐ AC caps small-body, anti-pad optimized, tight reference
- ☐ Connector launch + breakout tuned for return loss
- ☐ Channel sim (IBIS-AMI) against the Gen 5 loss budget before fab
Need it designed?
PCIe Gen 4/5 is bread-and-butter high-speed digital work for us, channel-simulated and measured. Scope a project.
References
- PCI-SIG, PCI Express Base Specification Rev 5.0.
- Panasonic Megtron 6 datasheet (low-loss laminate).
- Simberian / channel-sim app notes on via stubs and backdrilling.
- IPC-2141A, Controlled Impedance Circuit Boards.