PDN target impedance, from scratch.

Why a target impedance at all

A digital load draws current in bursts. By Ohm’s law, a burst ΔI through the PDN impedance Z makes a voltage wobble ΔV = ΔI × Z. If that wobble exceeds the rail’s tolerance, the chip misbehaves. So the design rule is simply: keep Z below the value that turns the worst-case ΔI into an acceptable ΔV. That value is the target impedance.

Deriving Z_target

From the datasheet you need two things: the rail voltage and its allowed ripple (often ±3% or ±5%), and the worst-case transient current step (sometimes given directly, otherwise estimate it as a fraction — 50% is a common starting assumption — of max current).

Worked example — a 0.9 V core rail, ±5% ripple, drawing a 10 A transient step:

4.5 mΩ is aggressive — it tells you immediately this rail needs many low-ESL ceramics plus a solid plane pair, not three 0.1 µF caps. That’s the value of computing it first: it sets the ambition before you place a single capacitor.

The frequency span that matters

You must stay under Z_target from DC up to the frequency where the package and on-die decoupling take over. Below ~1 kHz the VRM holds the rail. From there to ~tens of MHz, board capacitors and the plane do the work. Above that, only on-package/on-die capacitance is fast enough — the board can’t help, so don’t chase it.

Choosing the decoupling network

Each capacitor is a series RLC: it only looks capacitive below its self-resonant frequency (SRF), set by its capacitance and parasitic inductance (ESL). Above SRF it’s inductive and useless for decoupling. So you build a network whose members’ SRFs tile the band:

• Bulk (10–100 µF) handles low frequency near the VRM.
• Mid (0.1–1 µF) covers the MHz region.
• High-frequency (1–100 nF, smallest body, lowest ESL) placed right at the BGA balls.

The trap is anti-resonance: between two cap values, the inductance of one resonates with the capacitance of the next, creating an impedance peak that can punch above Z_target. Damp it by choosing values closer together, adding a controlled-ESR cap, or relying on plane capacitance. This is exactly what an AC PDN simulation reveals — and what a “0.1 µF everywhere” copy-paste hides.

The number of capacitors isn’t the spec. The impedance profile is. Caps are just how you shape it.

The PDN checklist

• ☐ Compute Z_target from V, ripple%, and ΔI before placing caps
• ☐ Identify the frequency band the board can actually influence
• ☐ Tile the band with bulk / mid / HF capacitor SRFs
• ☐ Place the smallest, lowest-ESL caps closest to the power balls
• ☐ Use a tight power/ground plane pair for plane capacitance
• ☐ Check for anti-resonance peaks (AC PDN sim) and damp them
• ☐ Confirm DC IR-drop leaves margin at the far-end load

Worked example: DDR5 1.0 V rail

Take a real DDR5 memory controller rail — 1.0 V supply, ±3% ripple budget, 2 A average current with a 200 mA transient step at 1 ns rise time. First, compute the target:

150 mΩ is relatively relaxed, but the 1 ns rise time means transient energy is present up to ~1/πt_r ≈ 320 MHz. The board can’t help above ~100–150 MHz, so you need to stay under 150 mΩ from DC to that edge.

Now build a three-tier network and check where each capacitor’s self-resonant frequency (SRF) lands:

• Bulk — 100 nF, 0402, ESL ≈ 400 pH: SRF = 1 / (2π√(LC)) = 1 / (2π√(100×10⁻⁹ × 400×10⁻¹²)) ≈ 25 MHz. Handles the mid-band region.
• Mid — 10 nF, 0402, ESL ≈ 300 pH: SRF ≈ 92 MHz. Covers the upper-mid band.
• High-frequency — 100 pF, 0201, ESL ≈ 100 pH: SRF ≈ 1.6 GHz. Extends coverage well past 300 MHz; placed directly at the BGA power ball.

The plane pair (say 4 mil core, 3 oz copper, 20 cm²) adds roughly 200–400 pF of distributed capacitance with very low ESL — important at the upper boundary where individual caps start going inductive. Running these numbers before choosing values prevents the common error of under-populating the 50–200 MHz window where DDR5 eye integrity lives.

Common mistakes — what actually goes wrong

These are the failure modes that show up repeatedly in PDN reviews:

1. Targeting at only one frequency. Designers compute Z_target, run a quick simulation at 10 MHz, see green, and ship. But the PDN is an impedance profile, not a point. Anti-resonance peaks at 40–80 MHz can blow past Z_target by 10× while the 10 MHz reading looks fine. Always sweep the full band (DC to at least 500 MHz for modern SoCs) and flag every frequency where |Z| > Z_target, not just the worst or most obvious one.
2. Ignoring via inductance on the return path. A single via from a power ball to the bulk cap plane adds roughly 0.5–1.5 nH of series inductance — more than the ESL of the cap itself. Designers often model caps as ideal or use the datasheet ESL figure, but omit the via stub. The result: the effective SRF of the cap shifts downward, the high-frequency coverage disappears, and the impedance rises exactly where the transient energy is concentrated. Use multiple vias in parallel (each via roughly halves the inductance) and model via inductance explicitly in your PDN tool.
3. Using datasheet capacitance at 25 °C and 0 V bias. MLCC capacitance degrades severely with DC bias and temperature. A 10 µF 0402 X5R cap at 1.0 V bias and 85 °C can measure 4–5 µF — less than half its rated value. If you sized your network assuming 10 µF, your low-frequency bulkhead has shifted upward in impedance, and the VRM handoff region is now undersupported. Always derate with vendor SPICE models at the actual operating voltage and temperature, not the spec sheet nominal.

Verifying in Altium’s PDN Analyzer

Once you have your Z_target calculated, use Altium’s PDN Analyzer (Reports → PDN Analyzer) to run an AC impedance simulation directly on your routed board. Overlay the calculated target impedance as a flat horizontal reference line — any frequency where the simulated |Z(f)| crosses above that line is a design violation to fix, not a cosmetic concern. For DDR5 rails specifically, pay attention to the 50–300 MHz window; that is where Altium’s simulation most often reveals anti-resonance peaks that hand-calculation misses.

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