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PDN target impedance, from scratch.

⌁ Pillar guide⌁ 9 min read⌁ Updated 2026-05⌁ By U. Costa, P.E.

TL;DR

The PDN’s job: keep the rail impedance below a target Z_target across frequency so transient current draw doesn’t move the voltage past its ripple budget.
Z_target = (V_rail × ripple%) / I_transient. Everything else — how many caps, which values — flows from this one number.
You don’t need every decade flat. You need it below Z_target from DC up to where the on-die capacitance takes over (often ~tens to low-hundreds of MHz).

Why a target impedance at all

A digital load draws current in bursts. By Ohm’s law, a burst ΔI through the PDN impedance Z makes a voltage wobble ΔV = ΔI × Z. If that wobble exceeds the rail’s tolerance, the chip misbehaves. So the design rule is simply: keep Z below the value that turns the worst-case ΔI into an acceptable ΔV. That value is the target impedance.

Deriving Z_target

From the datasheet you need two things: the rail voltage and its allowed ripple (often ±3% or ±5%), and the worst-case transient current step (sometimes given directly, otherwise estimate it as a fraction — 50% is a common starting assumption — of max current).

Z_target = (V_rail · ripple_fraction) / ΔI_transient

Worked example — a 0.9 V core rail, ±5% ripple, drawing a 10 A transient step:

Z_target = (0.9 · 0.05) / 10 = 0.045 V / 10 A = 4.5 mΩ

4.5 mΩ is aggressive — it tells you immediately this rail needs many low-ESL ceramics plus a solid plane pair, not three 0.1 µF caps. That’s the value of computing it first: it sets the ambition before you place a single capacitor.

The frequency span that matters

You must stay under Z_target from DC up to the frequency where the package and on-die decoupling take over. Below ~1 kHz the VRM holds the rail. From there to ~tens of MHz, board capacitors and the plane do the work. Above that, only on-package/on-die capacitance is fast enough — the board can’t help, so don’t chase it.

|Z(f)| held below 4.5 mΩ from DC → ~80 MHz; anti-resonance damped at 12 MHz

Figure 1 — A healthy PDN profile: flat-ish and below target across the band that the board can influence.

Choosing the decoupling network

Each capacitor is a series RLC: it only looks capacitive below its self-resonant frequency (SRF), set by its capacitance and parasitic inductance (ESL). Above SRF it’s inductive and useless for decoupling. So you build a network whose members’ SRFs tile the band:

Bulk (10–100 µF) handles low frequency near the VRM.
Mid (0.1–1 µF) covers the MHz region.
High-frequency (1–100 nF, smallest body, lowest ESL) placed right at the BGA balls.

The trap is anti-resonance: between two cap values, the inductance of one resonates with the capacitance of the next, creating an impedance peak that can punch above Z_target. Damp it by choosing values closer together, adding a controlled-ESR cap, or relying on plane capacitance. This is exactly what an AC PDN simulation reveals — and what a “0.1 µF everywhere” copy-paste hides.

The number of capacitors isn’t the spec. The impedance profile is. Caps are just how you shape it.

The PDN checklist

☐ Compute Z_target from V, ripple%, and ΔI before placing caps
☐ Identify the frequency band the board can actually influence
☐ Tile the band with bulk / mid / HF capacitor SRFs
☐ Place the smallest, lowest-ESL caps closest to the power balls
☐ Use a tight power/ground plane pair for plane capacitance
☐ Check for anti-resonance peaks (AC PDN sim) and damp them
☐ Confirm DC IR-drop leaves margin at the far-end load

Want it verified?

PDN design & power integrity is one of our core services — DC IR-drop, AC impedance, and resonance, coupled with thermal in TRM. Scope a project.

References

Larry Smith & Eric Bogatin, Principles of Power Integrity for PDN Design.
Istvan Novak, PDN resonance and decoupling papers (DesignCon).
Vendor PDN tools (target-impedance method) — TI, Intel, AMD app notes.
IPC-2152 (current density), IPC-2221 (spacing) for the DC path.