01
Low-inductance power loop
Gate and power loops measured in nH against the topology budget — drains, sources, decoupling and shunt-sense paths laid out for GaN/SiC fast edges.
Hard-switching, signed off.
Power-electronics PCBs fail in two ways: thermal and EMI. We design layouts that minimize loop inductance for GaN/SiC, hold the creepage and clearance UL requires, and ship with a TRM thermal report — not a spreadsheet of hopes.
to 200 Acontinuous rails
3 oz Curoutine; IMS available
IPC-2221creepage + clearance
±3 °CTRM vs measurement
The deliverables.
02
Isolation barriers done right
Reinforced barriers per IEC 60664-1 working voltage and pollution degree, with creepage modeled across the actual layout — not just the schematic.
03
Heavy copper / IMS / bus-bar
3 oz / 6 oz / heavy copper, IMS substrates, AlN where it earns its place, and bus-bar landings sized to the actual fault current, not a typical.
04
TRM thermal sign-off
Steady-state, transient and fault thermal — heat-sinks, cold plates and forced air modeled in TRM. The report is the deliverable, not a footnote.
Built for this sector.
Standards we design to
- IPC-2221 / IEC 60664-1 (creepage / clearance)
- IPC-2152 (current capacity)
- UL 61010 / IEC 62368-1 (safety)
- EN 55011 / CISPR 11 (EMC emissions)
- IPC Class 2 / 3, J-STD-001
Topologies + devices
- GaN HEMT half-bridge + totem-pole PFC
- SiC MOSFET inverters + DC/DC
- Synchronous buck / boost / SEPIC to 200 A
- LLC + phase-shift full-bridge
- Three-phase motor drives
Thermal + mechanical
- TRM-backed sign-off, IR-correlated
- IMS and aluminum-core MCPCB
- Bus-bar attach and press-fit
- Cold-plate and heat-sink integration
- 3 oz / 6 oz / heavy copper
A 120 A buck stage that stopped melting.
The brief
A 120 A 12 V → 1 V buck stage for an AI-accelerator board was running ~18 °C hotter than spec at full load and ringing badly at the gate.
What we did
- Re-laid the gate loop into a flat ~1.8 nH path with a polymer cap directly at the source pin — gate ring dropped by ~60%.
- Widened the inductor return through copper coins; TRM predicted ~12 °C drop, bench measured ~11 °C.
- Added a current-density verdict (peak < 200 A/mm² in the bottleneck) to the sign-off pack.
Outcome
Full-load Tmax dropped ~11 °C measured, gate ringing under spec, board signed off against an IR-correlated TRM report.
Common questions.
Heavy copper or IMS — which do I need?
Heavy copper buys you current capacity; IMS buys you thermal conduction. We model both in TRM and show you the cost / thermal / manufacturability tradeoff in the quote — there’s a clear winner per board.
Can you do GaN / SiC layout?
Yes — that’s most of our power work now. The gate loop IS the design; if it’s much above a few nH you’ve already lost. We measure it, not assume it.
Do you do magnetics layout too?
Planar magnetics on the PCB stackup, custom inductor footprints and winding-on-PCB are all in scope — usually as part of the same engagement.
Sign off the power stage.
Loop inductance measured, thermal proved, creepage clean. Fixed-fee band in 60 seconds.