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QFN thermal pad design — what actually moves Tj.

⌁ Thermal⌁ 8 min read⌁ Updated 2026-05⌁ By U. Costa, P.E.

TL;DR

The exposed pad is the dominant heat path on a QFN — through the pad, into the vias, into the plane. Get that chain right and silkscreen-level tweaks don’t matter.
Solder void fraction is the silent killer. A pad at 50% voiding can run 15–25 °C hotter than the same pad at 10%. Control it with a windowpane paste pattern, not one big aperture.
Vias matter, but the layer-2 copper area they dump into matters more above ~2 W. Don’t trade plane area for via #13.

The heat path

For a power QFN, ~80–90% of the heat leaves through the bottom exposed pad, not the leads or the case top. The series chain is: junction → die-attach → exposed pad → solder joint → PCB pad → thermal vias → inner/bottom copper → ambient. Every link is a resistance; the two you fully control are the solder joint quality and the copper geometry.

Paste coverage and voids

A single large paste aperture over the exposed pad outgasses during reflow and traps voids — pockets of air with ~1/10,000th the conductivity of solder. The fix is a windowpane (segmented) paste pattern: split the aperture into a grid of smaller openings (typically 60–80% total coverage) with channels for flux outgassing. This routinely drops void fraction from 40–50% down to 10–15%.

Effective pad resistance scales roughly with 1 / (1 − void_fraction) — halving voids from 50% to 25% is worth a real, measurable Tj drop.

Windowpane paste · ~70% coverage · 12% voids · Tj −18 °C vs. single aperture

Figure 1 — Segmented paste reduces voiding; the Tj delta vs. a single aperture is measurable, not cosmetic.

The via array (and the plane behind it)

Standard practice: a grid of 0.2–0.3 mm vias under the pad, ~1 mm pitch, plated (or filled-and-capped to avoid solder wicking). But the array’s resistance saturates fast — see Proximity over Quantity. The rule that holds up in measurement: get ~9–12 good vias, then spend your effort enlarging the contiguous layer-2 copper, not adding via #20.

If the vias aren’t filled, use a windowpane on the pad anyway and tent the via tops on the opposite side, or you’ll wick solder down the barrels and starve the joint.

You can’t fix a 45% voided thermal pad with more vias. Fix the paste first, then the copper.

QFN thermal pad checklist

☐ Windowpane paste, 60–80% coverage, outgassing channels
☐ 9–12 thermal vias, 0.2–0.3 mm, ~1 mm pitch
☐ Vias filled-and-capped, or tented opposite side to stop wicking
☐ Layer-2 copper ≥ 4× package footprint, contiguous, no splits
☐ Reflow profile tuned for the pad’s thermal mass
☐ Verify void fraction by X-ray on first article (< 25%, ideally < 15%)
☐ TRM sim at worst-case ambient before release

Want it verified?

Thermal-pad and via design are part of every PhySignoff engagement, with a TRM report correlated to measurement. Scope a project.

References

JEDEC JESD51 series, thermal measurement standards.
TI AN-1187 / SLUA271, QFN/LLP thermal and assembly guidance.
IPC-7093, Design and Assembly Process Implementation for Bottom Termination Components.
PhyCircuit, “Proximity Over Quantity,” 2025.