Stackup design — the rules of plane integrity.

What “plane integrity” actually means

Every high-speed signal’s return current flows in the reference plane directly beneath it — not somewhere convenient, not “in the ground generally,” but on the specific patch of copper an inch or so wide that runs directly under the trace. If that patch is broken — a slot, a gap from an antipad, a different net — the return current has to detour. The detour produces three predictable problems: extra inductance (slower edges, ringing), radiated EMI (the detour creates a loop antenna), and crosstalk (the return current finds a path through neighboring nets).

Plane integrity is the guarantee that every return-current path is short, direct, and continuous. It is not a guarantee you make in CAD — you make it in the stackup, by laying signal layers next to plane layers, and in the layout, by not routing across plane splits. The stackup is half the job.

The five non-negotiables

1. Every high-speed signal sees a continuous reference plane directly below (and above, for stripline)

“Directly below” means within a typical dielectric height — 4 to 10 mil — not 30 mil away with two layers of switching power rail in between. If the signal is on layer 1, layer 2 needs to be a solid ground (or a solid power rail, if it’s the rail the signal references on its source side). If the signal is on layer 3 between two planes, layers 2 and 4 are both planes, both continuous.

2. The return current’s reference is the same on both ends of any layer transition

When a trace transitions from layer 1 to layer 3 (through a via), the return current has to follow. If layers 2 and 4 are both ground, the return hops between them through whatever stitching vias you provided — ideally placed within ~40 mil of the signal via. If layer 2 is ground and layer 4 is power, the return has to traverse the plane gap, which means it has to find a decoupling cap at the right frequency — almost certainly the wrong one. Layer transitions inherit the discontinuity of the planes they bridge.

3. No plane splits under high-speed traces — or planned crossings only

Splits under high-speed signals are the most common stackup failure we re-spin. A trace crossing a 5-mil slot in its reference plane sees ~15 nH of extra inductance — enough to close the eye on PCIe Gen3 or to fail FCC by 6 dB. If a split must exist (split power planes for analog/digital separation are real), route any signals across it as a planned crossing with a clean reference (e.g., bridge with a stitching cap or with a different reference plane).

4. Symmetric stackup about the centerline

Copper distribution shrinks differently from FR-4 during the cure-and-cool press cycle. An asymmetric stackup — e.g., heavy outer-layer copper on top, thin power island on bottom — bows like a banana. The fix is mechanical, not electrical: mirror the copper layer count, the prepreg/core sequence, and the major fill ratios around the centerline. Asymmetry > 5% by mass tends to show up as > 0.5 mm bow on a 200-mm board, which kills BGA reflow yield.

5. Controlled-impedance layers pair with stable dielectric, not “whatever prepreg”

Z₀ = f(Dk, h). If the fab swaps in a different prepreg with Dk 4.3 instead of 4.05, your 50-Ω microstrip becomes a 48-Ω microstrip. For tight RF or DDR/PCIe sign-off, name the material on the fab drawing (Isola I-Tera, Megtron 6, Rogers 4350B for the RF layer) and call out the impedance tolerance (±5% or ±10%). The fab will respect named material on a controlled-impedance line and substitute on a “FR-4 generic” line.

How planes get broken — without anyone noticing

Plane breaks rarely show up as obvious slots. They sneak in:

• Antipad clearance gangs. Each BGA via removes a circle of plane. Cluster eight 14-mil antipads on 1 mm pitch and you have a Swiss-cheese plane — effectively a slot for any trace running across it on an adjacent signal layer. Re-route the trace, or stagger the BGA escape via grid.
• Plane keepouts for thermal islands. Some designers cut the plane around a hot QFN to “isolate it thermally” — usually a mistake (it just makes the QFN hotter and breaks return paths). Use copper pours and thermal vias to spread heat, not plane cuts.
• Power-rail islands stitched by chokes. Filter chokes between rails create an island. A signal running across the choke jumps two references. Always ask whether the signal needs to cross.
• Anti-pads from non-functional pads on inner layers. NFPs in older Altium / Pads outputs leave anti-pads everywhere, breaking the plane geometrically even though the via doesn’t connect there. Modern flows have an “NFP removal” option — use it.

Symmetry & warpage — the mechanical chapter

Warpage shows up in two places: BGA reflow yield and connector mating. A board that bows 0.7 mm across a 0.8-mm-pitch 484-ball BGA stops getting consistent solder joints in the corners — you lose yield without an obvious failure mode. The cure is mostly in the stackup:

• Mirror prepreg around the centerline. If layers 1–2 use 7628 prepreg, layers 5–6 should too.
• Match copper mass per layer pair. A 1 oz outer paired with a 2 oz inner on one side wants the same on the other.
• Avoid lone power islands — pour ground around them so the per-layer fill ratio matches the mirror layer.
• For boards above ~3 mm thick or with extreme asymmetry, talk to your fab about a backer board during reflow. It’s free advice from them; ask before you commit.

Worked example — a 6-layer DDR4 board

A real engagement we sign off regularly: a 6-layer DDR4-3200 board with an LPDDR4-style x32 bus, a 1.2 V rail, a 1.8 V rail, and FCC Class B compliance.

Three things make this 6-layer outperform many bad 8-layers:

• L3 DDR is a clean stripline. Continuous ground above (L2), the 1.2 V VDDQ plane below (L4) which IS the reference the DDR DQ lines return to. The decoupling caps at the IC pin close the AC return between the planes.
• L4 power islands don’t cross under L3 DDR. The 1.8 V island sits under the bus regulator + clock-recovery analog — not under DQ. We checked.
• Symmetric. 1 oz on every layer; 4 mil prepreg and core mirrored about the centerline (between L3 and L4). Total board thickness ~37 mil + 4×1 mil prepreg/core = nominal 1.6 mm. The fab quotes ±5% impedance against a named Isola I-Tera prepreg.

A short rubric

1. For each high-speed class (DDR, PCIe, USB 3, RGMII, RF), pick the signal layer and the reference plane(s) it depends on. Write them down.
2. Check that no two classes share a plane in a way that would break either return path. If two classes need different references, add layers; don’t negotiate harder.
3. Check the plane is continuous for the entire run of every high-speed trace.
4. Check transitions (via-up, via-down) have stitching vias to the new reference within ~40 mil.
5. Mirror the copper distribution about the centerline. If a fab survey says your board bows, you didn’t mirror enough.

That’s plane integrity. Layer count is the cost knob; plane integrity is the quality knob. Get them in that order.

If you only enforce one rule on a stackup, it’s “every high-speed signal sees a continuous reference plane directly underneath.” Almost every signal-integrity failure I’ve debugged on a marginal board traces back to a violation of that one sentence.

Tools mentioned

Φ Stack — canonical stackup builder · Impedance calculator · Φ Thermo — instant heatmap · 4 vs 6 vs 8 layer decision guide · DDR4 routing rules