Current carrying capacity.

Size a trace for a target current and temperature rise — or check the max current a trace can carry. Based on the IPC-2221 charts (conservative) with an IPC-2152 note.

⌁ Required trace width

—

mil

Cross-section—

Width (mm)—

Copper thickness—

IPC-2221 is intentionally conservative (it predates modern data). IPC-2152 typically allows ~30–50% more current for the same width because it accounts for board substrate conduction. For high-current sign-off, PhyCircuit validates with a TRM thermal simulation — see PhySignoff.

The formula

IPC-2221 fits the classic Preece-style current-vs-temperature-rise data to:

I = k · ΔT^0.44 · A^0.725

  I   = current (A)
  ΔT  = allowed temperature rise above ambient (°C)
  A   = trace cross-sectional area (mil²) = width(mil) × thickness(mil)
  k   = 0.048 (external traces) or 0.024 (internal traces)

Solving for area when you know the current:

A = ( I / (k · ΔT^0.44) )^(1/0.725)
width = A / thickness

Copper thickness from weight

Copper “weight” is really a thickness: 1 oz/ft² ≈ 1.378 mil (35 µm). So 2 oz ≈ 2.8 mil, 3 oz ≈ 4.2 mil. Plating adds to this on outer layers — confirm finished copper with your fab.

Why IPC-2152 is better (and why we still show 2221)

IPC-2152 (2009) used modern test boards and found IPC-2221 is over-conservative — real boards conduct heat through the dielectric and adjacent copper. For a 10 °C rise, IPC-2152 often allows 30–50% more current. We show the conservative IPC-2221 number here because it’s the safe default; for tight power designs we run the real number in TRM.

What this ignores

Adjacent copper pours and planes (they help — IPC-2152 accounts for them).
Vias in the current path (each via is a bottleneck — see the via current calculator).
Ambient above 25 °C (derate further — every 10 °C of ambient eats margin).
Pulsed vs continuous current (this assumes continuous DC).