4 vs 6 vs 8 layer PCB — how to pick.

The default question

Most layer-count debates conflate three things: how many signals you have to route, how many kinds of signals you have (each wanting a clean reference), and how many rails the PDN needs as continuous planes. A 4-layer board can route an enormous amount of low-speed signal — that’s not the limit. The limit hits when the second high-speed class shows up and there isn’t a second continuous reference plane to put it on.

Cost shape, not cost line

Layer-count cost isn’t linear. It’s a step function: each pair of layers adds a press cycle, often a drill cycle, and changes the impedance-controlled stackup options. For small-panel proto runs, the ratios we see (rough US prototyping rule of thumb, expect ±30% variance by fab and panel utilization):

The cost step from 4 to 6 is the biggest in percentage. From 6 to 8 it’s smaller. From 8 to 10/12 it grows again because of HDI/sequential lamination needs. Plan against the steps, not against a per-layer cost.

Plane integrity is the hidden driver

Pick your layer count by counting the reference planes you need to keep continuous, not by counting signals. A signal class — DDR, PCIe, USB 3, RGMII, RF — lives or dies by an unbroken reference plane directly under (and ideally directly over) it. If two signal classes need different references (a high-speed digital class wants a quiet GND; a switching power rail wants its own PWR plane), you can’t share without breaking one of them.

4-layer gives you one continuous plane and one power layer often broken into islands. 6-layer can give you two continuous grounds with one routing layer between them (a beautiful broadside stripline pair). 8-layer can give you two grounds and a continuous main rail. That’s why 8 is the floor for DDR4+ — not because the signals are fundamentally harder, but because they need both a clean GND and a clean V_DDQ.

Signal-class density rules

A rough rule that survives most projects:

• One high-speed class. 4-layer is usually fine (e.g., 1 GbE on the top with a clean inner ground).
• Two high-speed classes that share a reference. Still 4–6-layer (e.g., 1 GbE + USB 2 + slow SDIO).
• Two high-speed classes that need different references, OR a single class with tight differential pairs in a stripline. 6-layer minimum (e.g., USB 3 + 1 GbE + a switching buck near them).
• Three+ high-speed classes or any class above ~3 GHz Nyquist. 8-layer minimum (DDR4, PCIe Gen3, 10G Ethernet, MIPI D-PHY).
• Multi-class with multi-rail point-of-load and a high-density BGA. 10–12+. The BGA escape forces it (next section).

BGA escape + via cost

A 0.5 mm-pitch BGA forces 4–5 mil trace/space and a 4 mil drill if you want to escape every pin on inner layers. Below 0.5 mm pitch (0.4 / 0.35 mm), you’re into microvia / HDI territory and the conversation moves up to 8+ layers regardless of signal speed — you simply can’t fan out the pins on fewer routing layers. The BGA’s pitch and pin count often locks the stackup before the signal classes do.

A quick decision rubric

1. Count signal classes that need their own clean reference plane. Call that N.
2. Count rails the PDN needs as continuous planes (vs. fills). Call that R.
3. Minimum layer count is roughly 2 + 2·max(N, ceil(R/2)) + 2 (top + bottom signal + plane pairs).
4. If a BGA pitch ≤ 0.5 mm and pin count > ~300, add 2 layers regardless.
5. Add 2 more if anything is > 5 GHz Nyquist (loss budget, low-Dk material consideration).

The rubric isn’t religion — it’s a sanity check. If it says 6 and you have a clear reason to do 4, do 4 and document why. If it says 8 and you want to do 6, you’ll know what corner you’re cutting before you do it.

Layer count isn’t about how many signals you have. It’s about how many kinds of signals need clean references, and how many rails the PDN needs as planes. Count those, not the nets.

Want us to sanity-check it?

Stackup review is part of the PhySignoff tier and a quick win in PhyVerify. Scope a project on the RFQ scoper — band back in 60 seconds.