IR
DC IR drop
Resistance-network analysis from VRM pads to load ICs. Flags worst-case nodes against a configurable mV budget. Identifies traces and via paths that dominate the drop.
Φ PDN Extractor — AI-powered PCB power analysis.
Upload your board file once. Get DC IR drop maps, decoupling health checks, and multi-vendor BOM guidance — all from a single netlist or Gerber package. No Altium licence. No SIwave seat. Board data stays on your machine.
What you get in 60 seconds.
Here is a representative excerpt from a real analysis report. Every finding includes the net name, measured value, budget, pass/fail verdict, and a concrete fix you can apply directly in your EDA tool.
── BOARD SUMMARY ─────────────────────────────────
Format : Altium .NET v6
Nets : 842 total | 14 power nets identified
Layers : 14 | Copper weight: 1 oz (assumed)
── DC IR DROP ───────────────────────────────────
✓ VCC_3V3 max drop 12.4 mV budget 33 mV (1%) PASS
Worst path: VR1 → L3 → C47 → U7.VCC (R = 3.1 mΩ)
▲ VCC_1V8 max drop 28.1 mV budget 18 mV (1%) FAIL
Worst path: VR2 → L1 → U12.VDD (R = 7.4 mΩ)
Fix: add 4× via stitch at U12 power pad → est. drop 14.2 mV (PASS)
── DECOUPLING CHECK ────────────────────────────
✓ VCC_3V3 bulk 2×47μF mid 4×100nF HF 2×10nF ADEQUATE
▲ VCC_1V8 mid-band gap near U12 — missing 1μF @SRF 8 MHz
Suggest: Murata GRT155R61A105KE01D (0402, 1μF, 10V, X5R)
Place within 0.5 mm of U12 pin 14 (VDD)
── FINDINGS SUMMARY ────────────────────────────
3 findings | 1 critical (VCC_1V8 IR) | 1 advisory (decoupling)
❯ Report ready — estimated fix time: 15 min in Altium
Every finding cites IPC-2152, IPC-2141, or a datasheet SRF. No invented authority. When the math is approximate, we say so.
Four analyses, one upload.
The engine reads your board file, infers the PDN topology, and runs each check in seconds — no manual net assignment, no schematic redrawing.
⎁
Decoupling health check
Counts and classifies bulk, mid-band, and HF caps per rail. Cross-checks placement distance, ESL of the via path, and coverage at SRF. Suggests missing values with part numbers.
BOM
Multi-vendor BOM guidance
For every flagged cap or trace upgrade, the extractor proposes alternatives from Murata, TDK, Kemet, and Vishay — in stock, within footprint — with a one-click substitution rationale.
Z
Target-impedance check
Using your rail voltage and ΔI, the engine plots |ZPDN(f)| against the target impedance limit — the same method as the Φ Z-PDN visualizer, but driven from your actual board topology.
⎁ Input formats
Works with what you already have.
No export step, no format conversion. Drop the file your EDA tool already produces. ZIP packages are extracted and parsed layer-by-layer in your browser before any analysis is sent server-side.
Missing a format? Let us know — the parser list is short and growing.
| Format | Extensions | Support |
|---|---|---|
| Altium netlist | .NET | full |
| KiCad schematic netlist | .net | full |
| KiCad PCB layout | .kicad_pcb | full |
| OrCad netlist | .net, .dsn | full |
| Gerber + drill ZIP | .zip | zip |
| ODB++ | .tgz, .zip | beta |
⎁ Local-first
Your board never leaves your machine.
Proprietary designs are your crown jewels. The PDN Extractor is architected so your board data stays where it belongs — on your hardware, behind your firewall.
- File parsing happens in your browser. The raw board file is never uploaded.
- Only a compact netlist summary is sent for AI analysis — no copper geometry, no layer images.
- Self-host option: deploy the engine on your own server or local Docker container.
- ITAR / export-controlled programs: use the self-hosted path with zero external calls.
- No account required for the analysis. No telemetry on your net names or topology.
Local-first by design
Parse → summarise → analyse. The full board file never transits the wire.
Honest math, cited results.
DC IR: resistance network
Each copper segment is modeled as a resistor from geometry (length, width, copper weight). Via resistance is barrel-area based. The network is solved with modified nodal analysis (MNA) — same formulation as SPICE.
Decoupling: series-RLC per cap
Each capacitor is a series-RLC with SRF from C, ESL, ESR. Rack impedance is summed as parallel admittances. The same closed-form model powers the Φ Z-PDN visualizer and the target-impedance guide.
Cited, not hallucinated
Every finding references an IPC standard (IPC-2152 for current, IPC-2141 for impedance), a datasheet SRF, or is marked a PhyCircuit field heuristic — no invented authority. When the math is approximate, we say so.
Ready to run your board?
Paste a netlist or drop a ZIP. Analysis takes under 60 seconds. No account, no install.