DDR5 routing — what changed from DDR4.

What stayed the same

Before diving into the deltas, a grounding point: most DDR4 layout discipline carries directly into DDR5. Fly-by topology for address/command/clock (with write-leveling de-skew). Point-to-point DQ/DQS lanes with per-bit deskew and intra-pair tight matching (≤ ~1 ps). Continuous reference plane under every byte lane. No splits under the bus. Return vias within ~40 mil of every layer transition. The DDR4 guide covers the bulk of this; read it first if you haven’t.

What follows covers only the genuine DDR5 deltas — the things that will trip you up if you copy your DDR4 approach directly.

DFE + the loss budget

At DDR4-3200 (1600 MHz), the Nyquist frequency is 1.6 GHz. FR-4 insertion loss at that frequency is manageable: a 6-inch trace on standard stackup loses maybe 2–3 dB. The controller’s linear equalizer handles the residual ISI.

At DDR5-6400 (3200 MHz Nyquist) and above, FR-4 loss compounds fast. A 6-inch stripline on FR-4 at 3200 MHz loses 5–8 dB depending on copper roughness and laminate grade. Decision feedback equalization (DFE) is the answer: the controller looks at previous bits to predict and cancel ISI from the current bit. But DFE has limits — it can’t cancel beyond its tap count, and it can’t fix a channel whose eye is closed before equalization begins.

What this means for layout:

• Trace length budget tightens. DDR5 JEDEC specs allocate a channel insertion-loss budget (typically ≤ 7 dB at Nyquist for an unbuffered DIMM channel). You are spending that budget with every inch of trace, every via stub, every connector pin. Run the loss budget early in the design — not after routing.
• Via stubs matter more. A 40-mil via stub resonates at ~3 GHz — right in the DDR5-6400 Nyquist band. Backdrill or use blind vias for any DQ/DQS transition above DDR5-4800.
• Copper roughness is no longer ignorable. At 3200 MHz, surface-roughness loss adds 1–2 dB to conductor loss. For DDR5-6400 and above on a tight loss budget, spec low-profile (VLP) copper foil on signal layers.
• Laminate Dk/Df matters. FR-4’s Df of ~0.02 is fine to DDR5-4800. Above that, consider Megtron 6 (Df ~0.004) or equivalent for signal layers. You don’t need all-Megtron — a hybrid build (signal layers only) keeps cost reasonable.

On-DIMM PMIC placement

DDR4 power was simple: VDD and VDDQ on the motherboard, routed to the DIMM slot as plane rails. DDR5 moved power management onto the DIMM module itself. Per JEDEC JESD82-511, each DDR5 DIMM carries one PMIC (occasionally two on high-density RDIMMs for thermal load-sharing) that generates VDD (1.1 V), VDDQ (1.1 V), and VPP (1.8 V) for all DRAM devices on the module. A standard 9-device x72 RDIMM has 1 PMIC, not 9.

This is still a major mechanical change from DDR4 — instead of the motherboard managing DRAM power, you now have a switching regulator physically on the DIMM PCB with all the layout discipline that implies.

PCB layout consequences:

• PMIC placement relative to the DRAM array. The PMIC should be placed near the center of the DRAM array (or the dominant byte group) to equalize rail impedance to all devices. Longer distribution traces raise inductance between regulation and load, degrading power integrity at burst transitions.
• Quiet switching-node routing. PMIC switching nodes (typically 3–6 MHz switchers) generate noise that couples into DQ if routed nearby. Route the switching node away from the DQ byte lanes; use a ground guard if they must pass nearby.
• Input filtering at the PMIC. The PMIC input supply (V12 or V5 from the motherboard connector) needs local decoupling. Place 10 µF + 100 nF directly at the PMIC Vin pin; do not run more than ~5 mm of unfiltered supply trace before the first decoupling capacitor.
• Thermal consideration. The PMIC dissipates real power (efficiency ~85–90 %). On a dense DIMM this concentrates heat in one component. TRM-model the DIMM power budget at max load if junction temperature is a concern.

Sub-channel architecture

DDR4 presented a 64-bit data bus (72-bit with ECC) as a single channel. DDR5 splits this into two independent 32-bit sub-channels (A and B), each with its own command/address bus, clock, data bus, and strobe. The controller drives them independently — they can be different speeds, different power states, or even fail independently.

Layout implications:

• Treat them as two separate buses. Sub-channel A nets must not share reference planes, vias, or routing channels with sub-channel B nets in a way that would create crosstalk coupling. The JEDEC specification explicitly calls this out.
• Independent termination. Each sub-channel has its own fly-by chain and termination. The two chains should be routed entirely separately — not shared except at the connector pins.
• Independent clock trees. Clock for sub-channel A and clock for sub-channel B come from independent outputs of the clock driver. Route them on separate layers or with sufficient guard spacing to avoid coupling.
• Skew budget is per-subchannel. Byte-lane matching, strobe-to-DQ matching, and clock-to-command matching all apply within each sub-channel independently. Cross-subchannel timing is handled in silicon, not layout.

Fly-by and termination changes

DDR5 keeps the fly-by topology for the command/address/clock bus. The write-leveling flow is also retained. But two things changed on termination:

Host-side termination during reads is now more tightly specified. DDR4 defined both RTT_NOM (target-rank termination) and RTT_PARK (non-target-rank termination during reads) in JESD79-4 — read-path ODT was fully specified and widely used, not optional. The DDR5 change is that host/controller-side output impedance during read mode is now more precisely defined and testable than in DDR4, where the host-side termination state was less constrained. This affects your S-parameter sign-off: you need to model the channel with the controller-side impedance in its DDR5 read-mode state, which is now a specified test condition rather than a vendor-dependent assumption.

ZQ calibration is continuous. DDR4 ZQ calibration ran periodically. DDR5 runs it more frequently (background ZQ). This means the ZQ resistor network on the DIMM needs quieter placement — transitions on ZQ pin during calibration create small glitches that can couple to adjacent signals. Don’t route DQ signals directly alongside the ZQ calibration network.

On-die termination at the memory device is stronger. DDR5 DRAMs have lower effective termination impedance at high speeds, which helps absorb reflections on long stub topologies. This also means the bus is more forgiving of moderate impedance mismatches — but you still have the loss budget constraint above that limits channel length regardless.

Stackup implications

The DDR4 guide recommends 6-layer minimum for DDR4. For DDR5 at 4800 MT/s the same applies. For DDR5-6400 and above, especially on longer channels:

The DDR5 layout checklist

• ☐ Run channel insertion-loss budget at target speed before routing (FR-4 Df × length + via stubs)
• ☐ Backdrill any via stub > 30 mil on DQ/DQS for DDR5-6400+
• ☐ Per-DRAM PMIC within 15 mm of its DRAM; PMIC switching node routed away from DQ byte lanes
• ☐ Sub-channels A and B treated as independent buses — no shared planes/vias/routing channels between them
• ☐ Independent clock trees per sub-channel with guard spacing
• ☐ Continuous reference plane (no splits) under both sub-channels
• ☐ Intra-pair skew ≤ ~1 ps on DQS/CK for both sub-channels
• ☐ Per-bit deskew budget documented per byte lane per sub-channel
• ☐ ZQ calibration network isolated from adjacent DQ routing
• ☐ VLP copper specified on DQ/DQS layers at DDR5-6400+

The DDR4 discipline is necessary but not sufficient for DDR5. The extra work is: run the loss budget early, place the PMICs near their DRAMs, and treat the two sub-channels as completely independent buses.

Related tools and articles

DDR4 routing — the only rules that matter (prerequisite) · Stackup plane integrity · BGA escape routing · Impedance calculator · High-speed digital service