Learn/Articles/Decoupling strategy

Decoupling strategy — beyond “0.1 µF everywhere.”

⌁ PDN⌁ 9 min read⌁ Updated 2026-05⌁ By U. Costa, P.E.

TL;DR

A capacitor only decouples below its self-resonant frequency; above it, it’s an inductor. So you tile values to keep the PDN below target impedance across the band.
The real enemy is anti-resonance — the impedance peak between two cap values where one’s inductance rings with the next one’s capacitance. That peak, not the average, blows your budget.
Placement and mounting inductance often matter more than the cap value. The smallest, closest cap wins at high frequency.

Why a capacitor stops being a capacitor

Every real cap is a series R-L-C: capacitance C, equivalent series resistance ESR, and equivalent series inductance ESL (package + mounting). Its impedance is minimum at the self-resonant frequency:

f_SRF = 1 / (2π·√(L·C)) — above f_SRF the ESL dominates and |Z| rises. A 0.1 µF 0402 self-resonates near ~30–50 MHz; past that it does nothing for you.

This is why “0.1 µF everywhere” fails on fast loads — it leaves the rail undecoupled above ~50 MHz, exactly where modern logic draws its fastest current.

Choosing values against the impedance profile

Work the target-impedance method backwards: pick a set of values whose self-resonant frequencies tile the band you must cover, with enough of each to push |Z| under the target. In practice:

Bulk (10–100 µF) near the VRM for low-frequency droop.
Mid (0.1–1 µF) for the MHz region.
High-frequency (1–22 nF, smallest body) at the power balls.

Don’t space the values too far apart — wide gaps create deep anti-resonance peaks. Values within ~a decade, with the plane pair providing high-frequency capacitance, keep the profile flat.

|Z(f)| under target across band · anti-resonance at 18 MHz damped with controlled-ESR cap

Figure 1 — A healthy decoupling network: flat under target, anti-resonance peaks damped.

Placement & mounting inductance

At high frequency, the loop inductance from the cap to the IC power/ground pins dominates — and that’s set by layout, not the cap. Rules that hold up:

Smallest, highest-frequency caps closest to the power pins/balls.
Minimize the via-to-pad loop: vias at the pad ends, or via-in-pad for BGAs.
Tight power/ground plane spacing gives you “free” high-frequency plane capacitance with near-zero ESL.
Don’t share a long fanout trace between a cap and the pin it’s decoupling — that trace’s inductance defeats the cap.

The cap value sets where it helps. The mounting inductance sets how much. Layout is half the PDN.

Decoupling checklist

☐ Derive the target impedance first (V·ripple% / ΔI)
☐ Tile cap SRFs across the band the board can influence
☐ Keep values within ~a decade to avoid deep anti-resonance
☐ Smallest/HF caps at the power balls; via-in-pad for BGAs
☐ Tight plane pair for HF plane capacitance
☐ AC PDN sim to catch anti-resonance peaks; damp as needed

Want it verified?

Decoupling against a real impedance profile is core PDN design — DC + AC, coupled with thermal in TRM. Scope a project.

References

Smith & Bogatin, Principles of Power Integrity for PDN Design.
Istvan Novak, decoupling and anti-resonance papers (DesignCon).
Murata/TDK capacitor SRF and ESL datasheets.