PCB design glossary.
The terms that actually matter on a high-performance board — defined the way a senior EE would explain them to you, not the way a textbook would.
Signal integrity
- Controlled impedance
- A trace built to a target characteristic impedance (commonly 50 Ω single-ended, 100 Ω differential) by controlling width, dielectric height, and Dk. Required for any signal fast enough that reflections matter. Calculate it →
- Microstrip
- A trace on an outer layer with a reference plane below and air above. Lower effective Dk and lower loss than stripline, but more EMI-prone and less shielded.
- Stripline
- A trace on an inner layer sandwiched between two reference planes. Better shielding and SI than microstrip, at the cost of an extra layer and slightly more delay.
- Differential pair
- Two coupled traces carrying equal-and-opposite signals. Rejects common-mode noise and halves emissions. Needs tight intra-pair length matching and a controlled differential impedance.
- Skew
- Timing mismatch between signals that should arrive together — within a differential pair (intra-pair) or across a bus (inter-pair). Eats your timing budget directly. DDR4 matching →
- Crosstalk
- Unwanted coupling from an aggressor trace into a victim trace via mutual capacitance and inductance. Controlled by spacing (the “3W” rule of thumb) and tight return paths.
- Eye diagram
- An oscilloscope overlay of many bit periods. A wide-open “eye” means clean signaling; a closing eye means jitter, ISI, or loss are eating your margin.
- TDR (time-domain reflectometry)
- Sends a fast edge down a trace and measures reflections to map impedance vs. distance — how you find the via stub or stackup error that’s wrecking a high-speed net.
- Return loss
- How much of a signal reflects back due to impedance mismatch, in dB (more negative = better). The S-parameter that tells you if your 50 Ω is really 50 Ω.
- Insertion loss
- Signal energy lost traversing a channel (conductor + dielectric loss), in dB. Sets the reach of fast SerDes before equalization can’t recover the eye.
- Via stub
- The unused portion of a through-via below the layer a signal exits on. Acts as a resonant antenna that notches the channel — the #1 reason a fast signal mysteriously fails.
- Backdrilling
- Drilling out the unused stub of a plated via after fabrication to kill its resonance. Standard on PCIe Gen4/5 and 25G+ backplanes.
Power & thermal
- PDN (power distribution network)
- Everything between the regulator and the load pins — planes, vias, decoupling caps. Its job is to hold a low impedance across frequency so current bursts don’t move the rail. Deep dive →
- Target impedance
- The maximum PDN impedance that keeps voltage ripple within budget: Z = (V·ripple%)/ΔI. Every decoupling decision should flow from this one number.
- Decoupling capacitor
- A local charge reservoir that supplies fast current the regulator can’t. Each cap only helps below its self-resonant frequency, so you tile values across the band.
- IR drop
- Voltage lost to resistance along the power path (V = I·R). On low-voltage rails it eats tolerance fast — the reason power goes on planes, not traces. Calculate it →
- Thermal via
- A plated via under a hot component that conducts heat to an inner/bottom plane. Above ~2 W, plane area matters more than via count. Why →
- θJC (junction-to-case)
- Thermal resistance from a chip’s silicon junction to its case/pad, in °C/W. One link in the chain from junction to ambient; the board owns the rest.
- Copper pour
- A filled copper region (often ground) used for shielding, return paths, current spreading, and heat spreading. The unsung hero of both SI and thermal.
- Plane
- A solid copper layer (power or ground) that provides low-impedance current return and a continuous reference for controlled-impedance traces. Splitting one under a fast signal is a classic failure.
Fabrication
- Annular ring
- The copper ring around a drilled hole. Too thin and registration tolerance can break it out, causing opens. IPC class 3 requires no breakout. Class guide →
- Soldermask
- The (usually green) polymer coating that insulates copper and confines solder to pads. Thin slivers between pads flake off and cause bridging.
- Silkscreen
- The printed legend — reference designators, polarity marks, logos. Must not overlap pads, or it causes solder dewetting.
- DFM (design for manufacture)
- Designing within a fab’s real capabilities so the board builds with high yield. The fab’s DFM report flags violations. Translate one →
- Blind via
- A via from an outer layer to an inner layer that doesn’t go all the way through. Saves routing space; adds fab cost and sequential lamination.
- Buried via
- A via connecting only inner layers, invisible from outside. Used in dense HDI stacks; requires sub-lamination.
- Microvia
- A small laser-drilled via (≤ ~150 µm) between adjacent layers, the building block of HDI designs and fine-pitch BGA escapes.
- Aspect ratio
- Board thickness divided by drill diameter. High ratios make reliable plating hard — most fabs cap standard process around 8:1 to 10:1.
- Panelization
- Arraying multiple boards on one fabrication panel (with tabs or V-scores) for efficient assembly. Affects edge clearance and depaneling stress.
Materials
- FR-4
- The default woven-glass/epoxy laminate. Cheap and fine below a few GHz; its loss and Dk variation push high-speed RF designs to better materials.
- Dk / Df (dielectric constant / loss tangent)
- Dk sets impedance and propagation speed; Df sets dielectric loss. Low, stable Dk/Df is what you pay for in Rogers/Megtron at high frequency.
- Rogers laminate
- A family of low-loss, tightly-controlled-Dk materials (e.g. 4350B, 4003C) for RF/microwave and fast SerDes. Often used as a hybrid sub-stack to save cost.
- Prepreg
- B-stage glass-epoxy sheets that cure under heat/pressure to bond layers. Its thickness and Dk set inner-layer spacing and impedance.
- Core
- Fully-cured laminate with copper on both faces — the rigid foundation layers of the stack, alternating with prepreg.
- Copper weight
- Copper thickness expressed as oz/ft²: 1 oz ≈ 35 µm (1.4 mil). Heavier copper carries more current and spreads more heat. Current calc →
- Surface finish (ENIG / HASL / OSP)
- The coating that keeps exposed copper solderable. ENIG is flat and fine-pitch friendly; HASL is cheap but uneven; OSP is flat and low-cost but shorter shelf life.
Know the terms — now use them.
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