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Thermal via design rules — proximity over quantity.

⌁ Pillar guide ⌁ 14 min read ⌁ Updated 2026-05-22 ⌁ By U. Costa, P.E.

TL;DR

  • Above ~2 W per package, where your copper sits matters more than how many thermal vias you stitch.
  • The first 12 vias under a QFN reduce θJC by ~22 %. Vias 13–36 add another ~3 %. Diminishing returns are brutal.
  • A 25-mm × 25-mm copper plane on layer 2, directly under the QFN pad, beats 36 vias-into-a-tiny-pour by 6–9 °C in TRM simulation. We measured the same on bench.

Why this matters

You’ve seen the rule: “Add 9 thermal vias under your QFN’s exposed pad.” Most app notes say it. Most fabs draw it for you. Most reference designs ship with it. But for any package dissipating more than ~2 W, the via array is no longer the dominant thermal resistance — the copper area on the layer below is. This article is the data behind that claim.

The audience is anyone who has placed a DC-DC converter, an LDO, or a power MOSFET in a QFN/DFN pad and asked “is 9 vias enough?” The short answer is “the question is wrong.” The right question is “where does the heat go after it gets through the vias?”

The physics

The thermal path from a QFN junction to ambient goes through five resistances in series:

  1. θJC,top — junction to package case top (set by the silicon vendor).
  2. θJC,bot — junction to exposed pad (set by the silicon vendor, usually 1–4 °C/W).
  3. θpad→via — exposed pad through the via barrels.
  4. θvia→plane — vias into the inner-layer copper plane.
  5. θplane→ambient — copper plane spreading to the ambient (convection + radiation).

For a typical QFN at < 1 W, resistance #3 dominates. Adding vias drops it linearly until you saturate the plate. The classic “add 9 vias” rule is correct here.

But the moment the package crosses ~2 W, the spreading resistance #5 becomes comparable to #3. And #5 doesn’t scale with via count — it scales with effective copper area:

θspread ≈ 1 / (2·k·√(A·π)), where k = copper conductivity (385 W/m·K) and A = effective plane area (m²)

For A = 100 mm² (a 10×10 mm pour), θspread ≈ 7.3 °C/W. For A = 625 mm² (a 25×25 mm pour), θspread ≈ 3.0 °C/W. Three lines of math just saved you ~4 °C of margin — more than 36 extra thermal vias can give you.

Practical rules

  1. First, get your 9 vias right. 12 mil drill, 22 mil pad on the exposed pad layer, 8 mil annular ring on the layer-2 plane. Don’t tent. Plate-shut if your fab can do it without filling — otherwise leave them open.
  2. Then enlarge the layer-2 plane. Aim for at least a 4× package footprint of contiguous copper on layer 2, immediately below the pad. No splits, no thermal reliefs on the inner side.
  3. Drop redundant outer-layer copper. Pours on top/bottom outside the package help convection a little, but the spreading on inner layers dominates by 3–4×.
  4. Stitch the inner plane to bottom-layer copper if you can. Adds a second convective surface. Worth 2–4 °C at the cost of board real estate.
  5. Skip vias 13+. Use the area for the plane instead. We’ve simulated this 30+ times; you don’t gain meaningful θJC past ~12 vias on a typical 5×5 mm pad.

When you ignore them

Real failures we’ve cleaned up by re-spinning the via array and the copper geometry:

  • EV onboard charger, 80 W AC-DC stage. Stock reference had 8 thermal vias + a 12×12 mm pour. We re-spun to 12 vias + 28×28 mm pour. Drop: 14 °C at full load.
  • Industrial sensor PCB, 4 W LDO. Customer had pushed the rule to 36 vias to “be safe.” We removed 24 of them, doubled the plane area. Same θJC, half the board cost.
  • Telecom DC-DC, 25 A buck. The pour was sliced by a routing channel. Removing the channel and rerouting it to layer 3 dropped Tj by 11 °C without adding a single via.

TRM correlation

QFN 5×5, 9 vias, 10×10 mm pour · Tj = 112 °C
Figure 1 — Baseline. Standard “9 thermal vias + small pour” approach. TRM steady-state, 2.8 W dissipation.
QFN 5×5, 12 vias, 25×25 mm pour · Tj = 89 °C
Figure 2 — Same QFN, +3 vias, +6× copper area. 23 °C drop. Verified on bench within 1.4 °C.

We re-ran this experiment in TRM for 9 different geometries; the full sweep is in the Proximity Over Quantity publication. The summary correlation across 11 bench boards and their TRM models:

RMS error simulation vs IR measurement = 1.7 °C across all 11 boards (Tj range 71–118 °C).

The QFN thermal checklist

  • ☐ 12 vias on the exposed pad, 12 mil drill, 22 mil land
  • ☐ Vias plate-shut or filled-and-plated; no tenting
  • ☐ Layer-2 plane ≥ 4× package footprint, contiguous (no splits)
  • ☐ No thermal reliefs on the inner plane connection to the via stub
  • ☐ Optional: stitched to bottom-layer copper with ≥ 6 vias
  • ☐ Confirm θJC against vendor datasheet within ±15 %
  • ☐ Run a TRM sweep at expected ambient + 15 °C for margin
“Above 2 W, more copper beats more vias. Above 5 W, both matter, and you also need to start thinking about the chassis.”

Used by PhyCircuit

This is exactly the kind of analysis included in every PhySignoff engagement. If you’d rather not run the TRM sweep yourself, scope a project and we’ll do it on your board.

References

  1. IPC-2152, Standard for Determining Current Carrying Capacity in Printed Board Design, §6 (thermal characterization).
  2. JEDEC JESD51-7, High Effective Thermal Conductivity Test Board.
  3. Texas Instruments AN-1187, Leadless Leadframe Package (LLP) Thermal Considerations.
  4. Adam, J., TRM — Thermal Risk Management software manual, Adam Research, 2024.
  5. PhyCircuit, “Proximity Over Quantity: How Copper Plane Placement Outperforms Thermal Via Count in QFN Package Thermal Management,” 2025.