PCB DFM gotchas — the 12 fab-killers.

DFM (“design for manufacture”) sounds like a checklist box you tick before fab. In practice it’s the discipline that separates a board that yields 99% on the first article from one that ships 88% with a re-spin needed at 8 weeks. Every fab maintains a public capability sheet plus a private list of “stuff our DRC catches every week.” This article is the union of those private lists for the dozen issues we keep seeing in real designs — ordered by where they bite (assembly, field, fabrication) so you can plan against them on the next stack-up review.

Yield killers — they bite at assembly

1. Solder-mask slivers (the silent bridge cause)

What. The thin “web” of soldermask between two close pads — especially on fine-pitch QFN/BGA — gets thinner than the cure process can hold. The web flakes off during cure or handling, and the now-exposed copper between pads invites solder to bridge.

Why it kills. A failed mask leaves no insulation barrier between pads. Reflow paste flows freely across the gap — bridging fail, on a fine-pitch part nobody can rework easily.

The number. Standard fab process needs ≥ 3 mil sliver width; safer is 4 mil. Below 0.5 mm pitch you are routinely under this if you draw the mask the lazy way (gap = pad-to-pad clearance).

The fix. Pick SMD vs NSMD pad style deliberately. For 0.4 mm BGAs, use NSMD pads with a single mask opening that encloses the whole pad cluster (a “mask-defined window” with sliver elsewhere). Confirm against your fab’s specific sliver minimum; some Asian fabs hold 2.5 mil on a good day, most don’t.

2. Tombstoning from asymmetric thermal mass

What. A 0402 or 0201 chip cap lifts up on one end during reflow because one of its pads heats faster than the other. The capacitor pivots upright like a tombstone.

Why it kills. Imbalanced copper attached to the two pads — one pad lands on a wide ground pour, the other connects to a thin signal trace. The pour pad heats slower, its solder stays solid longer, while the trace pad reflows. Surface tension pulls the part upright off the lagging pad.

The fix. Make the two pads thermally symmetric. Use thermal relief on both, or no relief on both. If one pad must connect to a large pour, neck both pads to the pour through identical > 12-mil necks. Don’t let the asymmetry be invisible — the autorouter will gladly give you a 6-mil trace on one side and a flood fill on the other.

3. Insufficient annular ring

What. The copper ring around a drilled hole is thinner than the fab’s drill-to-pad registration tolerance.

Why it kills. Any drift in the drill registration breaks the ring entirely — the via barrel exits the pad through bare laminate, no electrical connection. Class 3 forbids any breakout; Class 2 allows 90° breakout (which is still a half-ring of contact).

The numbers. Standard fab process expects ≥ 4 mil annular ring on through-vias — meaning pad diameter ≥ drill + 8 mil. IPC Class 3 effectively wants ≥ 6 mil ring — pad ≥ drill + 12 mil. A 0.3 mm (~12 mil) drill therefore wants a 20 mil pad for Class 2 and 24 mil for Class 3.

The fix. Set pad diameters explicitly per drill in your padstack library. Don’t let the CAD tool “auto-shrink” to fit dense routing — that’s how you ship a design that works at 100% on lot 1 and 92% on lot 2 when the fab’s drill drifts 2 mil. See the IPC class guide for which class your board actually needs.

4. Via-in-pad without fill + plate

What. A via drilled directly through an SMD pad, without being filled with conductive (or non-conductive) material and plated over.

Why it kills. During reflow, paste melts on the pad and solder wicks down the via barrel. The pad ends up with a void; the joint above it is starved or cold. Worst on fine-pitch BGAs — you cannot inspect or rework these joints.

The fix. If the via lives in a pad, spec non-conductive fill + plate-over-copper (NCFPOC). The fab fills the via with epoxy, planarizes, and plates a flat cap of copper over the top. Adds ~$50–$200 to fab cost for a small board; non-negotiable for BGA pitches of 0.65 mm and below. The cheaper alternative — “tented via in pad” — reliably fails the joint.

Reliability killers — they bite in the field

5. Trace too close to the board edge

What. A signal, power, or plane copper feature inside the depaneling rout or V-score path.

Why it kills. Routing through outer copper lifts it; V-scoring cuts a few mil into the board on each side of the score line, taking any copper there with it. The board passes E-test, ships, and then fails in the field weeks later when a marginal trace fully fractures from vibration.

The numbers. 20 mil minimum copper-to-route-line for outer signal layers. 30 mil minimum if the panel uses V-score (the score cuts up to ~10 mil into the board). For plane layers, even more — 40 mil is conservative.

The fix. Set the design rule against the board outline as a hard rule, not a fab note. If you depanel by tab-rout, you can be tighter (≥ 15 mil); if you V-score, you can’t. The DRC will catch it if you tell it to.

6. Acid traps (sub-90° trace intersections)

What. A copper feature where two traces or a trace and a pad meet at an angle less than 90°.

Why it kills. During the etching pickle, etchant pools in the acute angle. The local etch rate accelerates — the trace gets notched on the inside of the angle. Notches concentrate stress and current, making the spot a long-term fatigue/electromigration site. Doesn’t always show up on E-test; shows up on thermal cycling.

The fix. Never go below 90°. Default to 135° (45° turns), which most CAD tools will do automatically. Audit any hand-edited routing, especially around fan-outs — the autorouter rarely violates this rule but hand cleanup often does.

7. Starved thermal connectors on copper pours

What. The “spoke” connectors from a pad to a ground or power pour are too thin, too few, or have too small a clearance.

Why it kills. Cold joints: too little copper bonded to the pour means the joint cools fast and the solder freezes before wetting the pour completely. Also weak mechanical bond — the joint fractures under thermal cycle.

The numbers. Standard thermal relief: 10-mil minimum spoke width, 4 spokes minimum per pad. For high-current pads (above ~1 A), go direct copper connection or 12-mil 8-spoke pattern. Through-hole connector pins also want thermals or hand-soldering becomes a fight.

The fix. Set thermal-relief parameters in the pour rules globally, then audit power and ground pin connections individually — the autopour usually gets it right for SMD pads and wrong for screw-terminal pads.

8. Silkscreen ink on solderable copper

What. Printed legend ink (silkscreen) touching an SMD pad, PTH annular ring, or via that needs to solder.

Why it kills. The ink causes solder dewetting — the wetted area shrinks back from the inked region during reflow, leaving a partial joint or no joint at all. On a fine-pitch part, the joint reads “ok” on AOI and fails six months later.

The number. ≥ 4 mil silkscreen-to-copper clearance on anything you intend to solder. Pads, vias-in-pad, annular rings of any PTH that gets soldered.

The fix. Run a “silkscreen over copper” DRC pass. Modern CAD tools have this rule; older flows often skip it. Pay extra attention to ref-des text squeezed near component pads — that’s where it sneaks in.

Process killers — they bite at fab

9. Drill aspect ratio over 10:1

What. Board thickness divided by drill diameter exceeds the fab’s plating-process limit.

Why it kills. Electroplating a long, thin barrel reliably requires good agitation of the bath through the hole. Beyond a certain aspect ratio, the barrel walls plate unevenly — you get thin spots that fail under thermal cycling, possibly months in the field.

The numbers. Standard process supports 8:1. Premium fabs do 10:1 reliably. Beyond 10:1 you should plan on HDI with microvias (≤ 1:1 aspect ratio each) and sequential lamination. A 2 mm board with a 0.2 mm via is 10:1 — right at the limit.

The fix. Run an aspect-ratio report from CAD against your stackup. If anything is over 10:1, redesign with larger drills (if pitch allows), reduce board thickness, or commit to HDI.

10. Copper balance and warpage

What. The total copper mass per layer is not mirrored about the centerline of the stackup. Layer 1 heavy, layer N light. Or one inner layer is full plane, its mirror is sparse trace.

Why it kills. Copper and FR-4 shrink differently during the press cycle. Asymmetric copper distribution makes the board bow during cool-down — visibly, like a banana. Then BGA reflow loses corner joints because the part can’t reach the board.

The numbers. Aim for < 5% mass imbalance per layer pair (about the centerline). Above that, expect > 0.5 mm bow on a 200 mm board — enough to drop BGA yield 10-30%.

The fix. Mirror your copper. If layer 2 is a solid GND, layer N-1 should be a solid plane too — if power doesn’t need that area, pour ground. For isolated power islands, pour ground on the mirror layer to match. See the stackup plane-integrity pillar for the symmetry chapter.

11. Plane islands (orphan copper fragments)

What. Small fragments of copper plane left disconnected after pour-clearance rules. Common around dense BGA antipads.

Why it kills. A floating copper island has no defined potential — it picks up nearby fields, can resonate, can build up enough voltage to fail HiPot testing or cause ESD events. Plus it’s a manufacturing waste: pours and processes copper that does no work.

The fix. Most CAD tools have a “remove orphan copper” or “minimum island area” rule — turn it on, set min area ≥ 25 mil². For islands you can’t remove (e.g., split-plane fragments), tie them to ground via a stitching via.

12. Missing or wrong drill chart

What. The drill chart in the fab pack doesn’t map to the drills actually in the Gerber, or the layer-pair information for blind/buried drills is missing.

Why it kills. The fab CAM operator picks the wrong drill bit, or skips a blind-via lamination step, or misreads the layer pair. The board comes back, you E-test it, opens everywhere. Re-fab cost is the whole lot.

The fix. Generate the drill report directly from CAD into the fab pack. Cross-check drill counts against the expected layer-pair count. For any blind / buried / microvia layer, label the layer pair explicitly in the fab notes (e.g., “L1-L2 microvia, L3-L4 blind, L5-L8 through”). When in doubt, send the fab a written drill table along with the Gerber, and ask for a confirmation email before they cut metal. Or drop your zip into Φ Gerber for an AI review that flags drill/layer mismatches.

The 12-item checklist

• ☐ Solder-mask slivers ≥ 3 mil (4 mil safer); mask design deliberate on fine-pitch
• ☐ 0402/0201 pad pair thermally symmetric (matching neck widths to pours)
• ☐ Annular ring ≥ 4 mil (Class 2) / ≥ 6 mil (Class 3); pad = drill + 8 / 12 mil
• ☐ Every via-in-pad spec’d as NCFPOC (non-conductive fill + copper plate)
• ☐ Outer copper ≥ 20 mil from rout line (30 mil with V-score)
• ☐ No sub-90° trace intersections (default 135° / 45° corners)
• ☐ Thermal-relief spokes ≥ 10 mil × 4 (12 mil × 8 for > 1 A pads)
• ☐ Silkscreen ≥ 4 mil clear of any solderable copper
• ☐ Drill aspect ratio ≤ 8:1 (10:1 with premium fabs); HDI above that
• ☐ Per-layer copper balance < 5% imbalance about the centerline
• ☐ Orphan copper removed or stitched to a defined net
• ☐ Drill chart present, matches Gerber, blind/buried layer pairs labelled

Most DFM “findings” are slight variations on these twelve. Get the twelve right and the fab DRC report stops being a re-spin trigger and starts being a sanity check.

Tools and articles mentioned

Φ DFM Translator — paste a fab DFM report, get a plain-English translation per item · Φ Gerber Review — drop a Gerber zip for an AI review · IPC Class 2 vs 3 guide — deciding which class your board needs · Stackup plane integrity — for the warpage chapter · Surface finish glossary entry