EMC for power supplies — layouts that pass first-time.

Why power supplies fail EMC

A switching power supply takes a slow DC voltage and turns it into a square wave with rise and fall times of single-digit nanoseconds (modern GaN/SiC) or tens of nanoseconds (legacy silicon). The Fourier series of a square edge with 5 ns transition extends to roughly 60–100 MHz with meaningful energy; faster edges push that into the hundreds of MHz. That’s right where CISPR 32 / 22 Class B starts limiting radiated emissions, and right above where conducted emissions (CISPR 32, FCC Part 15 Subpart B 150 kHz–30 MHz) are measured.

The switching node IS the noise source. You can’t make it slower without giving up efficiency. So the EMC problem is not “remove the noise” — it’s “don’t give the noise a path to radiate or conduct.” That path is the loop: any current path that encloses physical area becomes a magnetic-dipole antenna, with radiation efficiency that scales with the area enclosed times the di/dt. Tight loops are the cheapest filter ever invented.

Loop 1 — the gate loop

The gate driver feeds high di/dt pulses (peak ~A/ns through the gate-source capacitance of a power FET) through a loop comprising: driver output pin → gate trace → MOSFET gate → MOSFET source → return path back to the driver ground pin. The smaller the loop area, the lower the parasitic inductance, the faster and cleaner the switching transition. The bigger the loop, the more ringing on V_GS, more EMI, and more dissipation in the gate resistor.

Target: gate-loop inductance ≤ 5 nH for high-speed Si MOSFETs, ≤ 2 nH for GaN. Achieve it by placing the gate driver IC directly against the FET source pad — sometimes within 2 mm — and routing the gate return on the layer immediately below the gate trace, no other plane structures between them.

The return-via discipline. The driver ground pin must connect to the same local ground island that the FET source pin connects to, via at least two stitching vias within ~5 mm. This is the same return-via principle we cover in BGA escape routing — the geometry is different but the physics is identical: return-current path proximity controls loop area.

Loop 2 — the power loop

The power loop is the high-frequency commutation path: input cap → high-side switch → low-side switch (or freewheeling diode) → input cap. For a buck converter, when the high-side turns off and the low-side turns on, a current step traverses this loop at the switching frequency’s harmonics. The loop’s parasitic inductance times di/dt creates a voltage spike on the switch node that dominates radiated emissions above ~30 MHz.

Target: power-loop inductance ≤ 2 nH for ≥ 10 A switchers, < 1 nH for ≥ 50 A. The only way to hit this is a vertical loop — input cap on top layer, switch transistors on top, and ground return on the layer immediately below (layer 2), with the loop closing through tightly-spaced vias.

Two design rules follow. First, decoupling input caps go at the IC pin, not 5 mm downstream. Second, do not place vias inside the loop area that don’t carry the commutation current — they steal current and increase effective loop inductance. Treat the loop as a sacred geometry: nothing in it that isn’t part of the loop.

Loop 3 — the output / inductor loop

The inductor stores energy and releases it to the load. The ripple current through the inductor produces a magnetic field that radiates from the inductor body. This is the magnetic emissions source (B-field), distinct from the E-field from the switch node.

Three layout rules:

1. Orient inductor flux away from sensitive analog and ADC inputs. Most SMD inductors have a flux axis perpendicular to the PCB; some (toroids, shielded) confine it well; others (un-shielded drum cores) leak significantly. If you have an un-shielded part, place it at the corner farthest from the rest of the board.
2. Keep the loop area between the inductor and its output cap tight. Stage the cap right at the inductor pad with a short trace, then route to the load.
3. Magnetic shielding — a small grounded copper strip across the top of the package, or a metal can — for tight enclosures with sensitive RF nearby.

Loop 4 — common-mode

Common-mode noise rides on both rails together (referenced to chassis or earth) and conducts out via cables to the outside world — the dominant cause of CISPR 32 / FCC conducted-emissions failures. It is generated by the switch-node dV/dt coupling through stray capacitance to chassis ground.

Three controls:

• Y-caps from each rail to chassis ground at the input connector — 470 pF to 2.2 nF typical. They short the common-mode noise current locally so it doesn’t travel out the cable.
• Common-mode choke on the input rails. A 1–10 mH inductor with both rails wound in opposing directions presents high impedance only to common-mode signals; differential current sees a small leakage. Pick the choke whose Z(f) curve covers the band you need to attenuate.
• Chassis-ground bond — the connector shell, the PCB chassis-ground pour, and the enclosure must bond at low impedance at one well-defined place. Multiple bonds at high impedance create ground loops; one good bond is the cure.

Filter design without iteration

The classic trap is to design an EMI filter by guessing components and iterating against chamber data. The cheaper approach: predict the noise spectrum, predict the filter’s impedance, draw both against the spec line in one chart, and pick components that hit the attenuation gap with margin.

The noise spectrum from a switcher is well-approximated: a comb at the switching frequency and its harmonics, decaying ~20 dB/decade above the corner (or ~40 dB/decade if you have a clean continuous-conduction-mode design). The conducted-emissions spec is a line on the same plot — CISPR 32 Class B is 66 dBµV from 150 kHz to 500 kHz, dropping to 50 dBµV above 5 MHz; FCC Part 15 Subpart B is similar.

Subtract one from the other and you have the attenuation requirement vs frequency. Pick a filter topology whose insertion loss covers the required attenuation with ~10 dB margin. For most low-current designs an L-C-L (π filter) works; for higher current swap the second L for a common-mode choke. Use the Φ Z-PDN visualizer to plot the differential-mode part of the filter Z vs frequency — the same tool that designs your PDN also predicts your filter’s attenuation.

The pre-compliance layout checklist

• ☐ Gate loop ≤ 5 nH (Si) / ≤ 2 nH (GaN), driver IC within 2 mm of FET source
• ☐ Power loop vertical (top layer + L2 ground), input cap at IC pin, ≤ 2 nH for ≥ 10 A
• ☐ Switch-node copper minimized — just enough for current; no larger than necessary (it’s an antenna)
• ☐ Inductor flux axis pointing away from analog / RF; un-shielded inductor at board corner
• ☐ Input filter at the connector, before any traces split off
• ☐ Y-caps from each rail to chassis ground at the connector, ≤ 4.7 nF total to comply with leakage limits
• ☐ Common-mode choke sized against the noise-vs-spec attenuation curve, not a guess
• ☐ Chassis-ground bond at one well-defined low-impedance point
• ☐ No trace crossing under the switch node on adjacent layers (induced coupling)
• ☐ Continuous ground reference under every signal that exits the supply

EMC chambers are expensive. Layout discipline is free. Most “EMC problems” are loop-area problems that were preventable in the schematic capture phase — if you knew which loops mattered.

Tools and articles mentioned

Φ Z-PDN — plot filter Z vs frequency vs spec · Φ Stack — plane integrity under the switcher · Φ Thermo — thermal sanity after filtering · PDN target impedance · Stackup plane integrity · High-power service · Automotive (CISPR 25)