Differential pair matching — how tight is tight enough?
TL;DR
- Intra-pair (P vs N) skew converts a clean differential edge into common-mode noise + EMI. Keep it tight — typically < 5 ps (≈ 30 mil), < 2 ps for 10G+.
- Inter-pair (lane-to-lane) matching only needs to fit the protocol’s deskew window — far looser, and the controller often removes it.
- Match at the source of the mismatch (the bend, the via, the breakout), not with a giant serpentine 3 inches downstream.
Two kinds of skew — don’t conflate them
Engineers burn enormous router time matching the wrong thing. There are two distinct requirements:
- Intra-pair skew — the length difference between the + and − of one pair. This is the one that hurts: any mismatch shifts the differential crossing, generates common-mode current, and shows up as EMI and jitter. Budget it tightly.
- Inter-pair / bus skew — the difference between one pair and another (or to a clock). Protocols like PCIe and USB include receiver deskew that absorbs generous amounts of this. Matching every lane to ±5 mil board-wide is usually wasted effort.
The budget math
Propagation delay on a stripline is roughly 150–180 ps/inch, so 1 ps ≈ 6 mil. Convert your timing budget to length:
Δlength (mil) ≈ skew_budget (ps) / tpd (ps/mil) — at ~0.17 ps/mil, a 5 ps intra-pair budget = ~30 mil of allowed mismatch.
For a 1 mil-accurate router that’s trivially achievable — the real intra-pair skew usually comes from asymmetric bends and via transitions, not from forgetting to length-match the straight runs.
Bump compensation at the bend: outer leg shortened locally, skew < 1 ps
Fixing skew without wrecking the pair
- Bump/jog at the bend. On a turn the outer trace is longer; add a small compensating bump to the inner trace right there. Keeps the pair tightly coupled.
- Match at the breakout. BGA escape is where most intra-pair skew is born — equalize within the escape, not 2 inches later.
- Serpentine only as a last resort, and keep the wiggle amplitude small (≤ 3× trace width) so you don’t detune the differential impedance or create a stub.
- Symmetric vias. If one of the pair changes layers, change both at the same point with identical via geometry.
Tight intra-pair, loose inter-pair. Match where the skew is born, not downstream. That’s 90% of differential routing.
Checklist
- ☐ Intra-pair < 5 ps (≈ 30 mil); < 2 ps for 10G+ SerDes
- ☐ Compensate skew at bends/breakouts, not with long serpentines
- ☐ Symmetric, co-located via transitions for both legs
- ☐ Inter-pair matched only to the protocol’s deskew window
- ☐ Continuous reference plane under the whole pair
- ☐ Serpentine amplitude small enough to preserve Zdiff
Need it routed?
This is core high-speed digital work — DDR5, PCIe Gen5, 100G, matched and verified. Scope a project.
References
- PCI-SIG, PCIe Base Specification (lane deskew).
- Howard Johnson, High-Speed Digital Design.
- IPC-2141A, Controlled Impedance Circuit Boards.