01
Impedance-controlled stackup
Per-layer dielectric/copper plan that actually hits 50 Ω SE and 100 Ω diff, confirmed against your fab’s process.
Boards that train on the first article.
DDR5 at 6400 MT/s. PCIe Gen 5. 100G SerDes. We route the hard interfaces with controlled impedance, matched skew, and pre-layout SI — and we prove it with measured eye diagrams.
6400 MT/sDDR5 trained
±3 pstypical pair skew
50/100 Ω±5% controlled Z
14+layers routine
The deliverables.
02
Topology + termination
Fly-by for DDR, point-to-point for SerDes, with the right series/parallel termination and Vtt strategy.
03
Length + skew matching
Byte-lane and pair matching to spec, with intra-pair skew minimized at the via and the BGA escape.
04
Pre-layout SI
Channel sims for the critical nets; we tune trace geometry before we commit copper, not after the re-spin.
Named, not generic.
Memory
- DDR3 / DDR3L
- DDR4 @ 3200 MT/s
- DDR5 @ 6400 MT/s
- LPDDR4/5
- Fly-by + T-topology
Serial high-speed
- PCIe Gen 3 / 4 / 5
- 100G SerDes (NRZ + PAM-4)
- 10/25G Ethernet, SFP+/SFP28
- SATA / SAS
Peripheral + display
- USB 3.2 / USB-C alt-mode
- HDMI 2.x, DisplayPort
- MIPI D-PHY / C-PHY
- CSI / DSI camera + display
14-layer DDR5 that wouldn’t train.
The brief
A vendor design topped out at DDR5-4800 and the team couldn’t find why. We were brought in to diagnose and re-spin.
What we found
- Stackup mistuned by 7 mil — Z0 drifted to 47 Ω against a 50 Ω target.
- BGA escape added uncontrolled length and a via stub on the strobe.
- Intra-pair skew of 9 ps from a lazy serpentine at the connector.
Outcome
Re-tuned stackup, back-drilled the offending vias, re-matched at the escape. Trained at full 6400 MT/s on first article; eye height improved 38%.
Common questions.
Do you do the SI simulation or just the layout?
Both. We run pre-layout channel sims to set geometry, then post-layout to confirm. For sign-off-grade SI (full IBIS-AMI, compliance masks) we partner or scope it explicitly.
Which CAD tool?
Altium Designer primarily; Orcad and Mentor Xpedition on request. We deliver native + fabrication outputs.
Can you hit a 4-week deadline?
For a known-good schematic, often yes — the RFQ scoper flags rush feasibility instantly.
Route it right the first time.
Senior EEs on every high-speed net. Fixed-fee band in 60 seconds.