PhyDesign
Design$8k–$35k/ board
- Schematic capture or review
- Layer stackup design
- Placement + routing
- DFM/DFA-clean fab pack
- Altium, Orcad, or KiCad
When: you need a board designed correctly from scratch.
Scope this →The board, done by engineers.
DDR5. PCIe Gen 5. 100G SerDes. 200 A rails. mmWave RF. Thermal sign-off backed by TRM simulation. We don’t sub-contract the layout to interns.
Pick the depth of engagement.
Indicative bands. Final quote depends on layer count, signal classes, and turn-around. The RFQ scoper gives you a real number in 60 seconds.
PhyVerify
Verify$3k–$15k/ board
- Independent design review
- Stackup + impedance check
- Signal-integrity sanity (lite SI)
- PDN review (DC + AC)
- TRM thermal pre-check
When: your team did the layout — you want a senior pair of eyes.
Scope this →PhySignoff
Sign-off$12k–$45k/ board
- Full TRM thermal report (named deliverable)
- PDN AC + DC analysis
- SI eye diagrams + return loss
- EMC pre-compliance pass
- Reliability + IPC class verdict
When: “won’t melt in Phoenix” is on the spec sheet.
Read more →Specifics, not vibes.
We list what we’ve actually shipped — not what marketing wants to claim.
High-speed digital
- DDR4 @ 3200 MT/s
- DDR5 @ 6400 MT/s
- PCIe Gen 4 / Gen 5
- USB 3.2 / USB-C alt-mode
- 100G SerDes (NRZ + PAM-4)
- 10G Ethernet, SFP+
- MIPI D-PHY / C-PHY
RF & microwave
- 2.4 / 5 / 5.8 GHz Wi-Fi
- BLE, Zigbee, Thread
- LoRa, sub-GHz
- 5G sub-6 / mmWave
- Rogers 4350B / 4003C
- GCPW + microstrip + SIW
High-current power
- Up to 200 A continuous
- 3 oz copper, IMS, AlN
- Bus-bar attachment
- EV / industrial / telecom
- GaN + SiC topologies
- PoE/PoE++ injectors
Thermal sign-off
- TRM-backed reports
- Steady-state + transient
- QFN / DFN / BGA thermal
- Heat-sink + cold plate
- IR-correlated sims
- IPC class 2 / 3 / 3A
Rigid-flex & specialty
- 2–8-layer rigid-flex
- Bookbinder for tight bends
- Chip-on-board, COF, COB
- Embedded resistors / caps
- Aluminum-core MCPCB
Reverse engineering
- Gerber to Altium re-create
- EOL part replacement
- Layer stripping + scan
- Schematic extraction
- Design recovery / cleanup
Specialist pages.
High-speed digital →
DDR5, PCIe Gen5, 100G SerDes, USB-C, MIPI.
RF & microwave →
Wi-Fi, BLE, 5G sub-6, mmWave intros.
High power →
To 200 A, heavy copper, IMS, GaN/SiC.
PDN design →
Target impedance, decoupling, IR-drop.
Thermal sign-off →
TRM-backed report. Our flagship.
The standards your sector demands.
Every industry has its own rulebook. We design to it from the first stackup — see the per-sector pages, or the industries hub.
Medical →
IEC 60601-1 isolation, low-noise analog, IPC Class 3, DHF-ready.
Automotive →
AEC-Q parts, ISO 26262, LV124, CISPR 25, thermal sign-off.
Aerospace & defense →
DO-254, MIL-PRF, MIL-STD-810/461, Class 3/3A, space-grade options.
IoT & connected →
Antenna tuning, <1 µA sleep, FCC/CE pre-cert, volume-cost.
Power electronics →
To 200 A, GaN/SiC gate-loop, IPC-2221 creepage, TRM thermal.
Robotics & motion →
Motor drives, mixed-signal, CISPR 11, functional safety aware.
Five steps. No mystery.
-
01
Discovery
30-minute call (or async RFQ). We pin down interfaces, layer count, signal classes, certifications, deadline, and what success looks like.
-
02
Stackup & SoW
You get a layer stack, a controlled-impedance plan, a fixed-fee proposal, and a calendar.
-
03
Layout
Senior EE on the schematic and the board. Weekly review with screen-share. No surprises.
-
04
Sign-off
TRM thermal report + DRC + DFM + PDN. We hand-walk the report — you’re not reading numbers alone.
-
05
Hand-off
Fab pack, BOM, ODB++, assembly drawings, README. We’re on call for first-article and bring-up.
Drop the spec. Get a real number.
The RFQ scoper estimates your project in under 60 seconds. A senior EE confirms within 24 hours.