Target-impedance budget
Z(f) derived from the load’s transient current and ripple spec — the number every decap decision flows from.
We derive your target impedance from the silicon, place decoupling that actually works, kill plane resonances, and prove the rail with DC IR-drop and AC PDN analysis.
Z(f) derived from the load’s transient current and ripple spec — the number every decap decision flows from.
Cap values, counts, and placement chosen against the impedance profile — not a copy-pasted “0.1 µF everywhere.”
Layer-by-layer voltage drop across the PDN so the far-end rail still meets tolerance at full load.
Impedance-vs-frequency with anti-resonance peaks identified and damped before they bite.
A telecom DC-DC was failing intermittently under load. The team suspected the regulator; it was the plane.
Re-routed the offending channel to an inner layer, restored the plane, and re-built the decap network against the target impedance. IR-drop fell to 41 mV; the intermittent fault disappeared.
Helpful but not required. We can derive a target impedance from the datasheet’s transient-current and ripple specs and refine if models are available.
Related — TRM couples PDN and thermal (copper resistance rises with temperature). For mission-critical boards we bundle both into PhySignoff.
Yes — that’s a PhyVerify engagement. We’ll tell you where the rail is at risk and what to change.
Target-impedance-driven PDN design, DC + AC verified. Fixed-fee band in 60 seconds.