Via stubs and backdrilling — when and how.

What a via stub is

A plated through-hole (PTH) via drills the full board thickness regardless of which layers it connects. If a signal enters on layer 1 and exits on layer 4 in a 10-layer board, the via barrel continues from layer 4 through layers 5–10 with no electrical connection — that continuing barrel is the stub. It is plated copper, open at the bottom (the drill exit), hanging off the signal path at the exit layer.

Both the connected portion and the stub contribute parasitic capacitance and inductance to the channel. The stub adds more.

Two distinct effects: don’t confuse them

The via stub literature conflates two different physical effects that operate at different frequency ranges. Separating them prevents confusion about when and why to backdrill.

Effect 1 — Capacitive discontinuity (all frequencies, worsens with f). The via geometry (pad, antipad, and barrel) creates a lumped parasitic capacitance in shunt across the signal path. This capacitance reduces the local impedance below Z₀, reflecting energy back toward the driver and causing a measured insertion-loss dip. This effect worsens as frequency increases (X_C = 1/ωC decreases) and is the dominant concern at DDR5 and PCIe Gen4/5 speeds. A longer stub means more capacitance and a worse discontinuity.

Effect 2 — Quarter-wave stub resonance (high frequencies only). At the specific frequency where the stub length equals a quarter-wavelength (electrically), the stub resonates and presents a near-short to the signal, creating a deep notch in S21. For typical PCB stub lengths (10–60 mil), this resonance occurs at very high frequencies — see the table below. This effect only becomes relevant at 100G+ SerDes (Nyquist ≥ 25–28 GHz) and is not the concern at DDR5 or PCIe Gen5 speeds.

Stub resonance — the formula (and why it’s not the DDR5/PCIe problem)

The quarter-wave resonance frequency of a shorted stub is:

Where c₀ = 3×10⁸ m/s, L_stub is the stub length in meters, and ε_eff ≈ ε_r of the dielectric (4.3 for FR-4, giving √ε_r ≈ 2.07). The resonance creates a deep notch in S21 at f_stub.

Computed resonant frequencies for FR-4 (ε_r = 4.3):

Cross-check: Bogatin’s “Signal and Power Integrity — Simplified” gives ~1.5 GHz for a 1-inch (25.4 mm) stub in FR-4 (ε_r ≈ 4.0), which extrapolates to ~38 GHz for a 40-mil stub. Consistent with the table above.

Key implication: a stub would need to be ~500 mil long to resonate at DDR5-6400 Nyquist (3.2 GHz). That doesn’t exist in practice. When engineers backdrill PCIe Gen5 or DDR5 boards, they are reducing capacitive discontinuity, not preventing a resonant notch.

Via capacitive discontinuity — the real DDR5/PCIe concern

The via capacitance model: a PTH via pad and antipad form a structure with parasitic capacitance C_via ≈ 1–5 pF depending on drill size, pad diameter, antipad diameter, and copper layer count. The stub adds additional capacitance proportional to its length.

This capacitance creates a shunt element across the signal path. At frequency f, its impedance is 1/(2πfC), which falls below Z₀ (50 Ω or 100 Ω diff) when f is high enough. The reflection coefficient from the via discontinuity becomes measurable around 1–5 GHz even for modest C_via values.

Practical consequences:

• At PCIe Gen3 (4 GHz Nyquist): a via with C_via = 2 pF contributes a small but measurable impedance dip; typically within budget on short channels.
• At PCIe Gen4 (8 GHz Nyquist): via capacitance becomes a meaningful portion of the channel insertion-loss budget; via optimization starts to matter.
• At PCIe Gen5 (16 GHz Nyquist): via capacitance is a primary design constraint. PCIe Gen5 channel budgets often require backdrilling to reduce the via stub’s capacitive contribution, in addition to using small-geometry pads and optimized antipads.
• At DDR5-6400 (3.2 GHz Nyquist): modest via capacitance from short stubs (≤ 20 mil) is usually within budget on typical board lengths. Backdrilling is not required for standard DDR5-6400 on well-designed boards.

How to reduce via capacitance: smaller pad diameter, larger antipad clearance, fewer copper layers the via traverses, shorter stub (backdrilling), or back-to-back vias that share the pad.

When each effect actually matters

• < 3 Gbps: both effects negligible. Via geometry is a second-order consideration.
• 3–10 Gbps (PCIe Gen2–3, USB 3.x, DDR5-4800): via capacitance starts to matter on long channels or densely-loaded buses. Optimize pad/antipad geometry; backdrilling usually not required.
• 10–20 Gbps (PCIe Gen4–5, DDR5-6400): via capacitance is a primary channel-budget item. Optimize via geometry; plan for backdrilling on long channels or when the channel budget is tight. Stub resonance is not the concern — it’s the capacitance.
• 25+ Gbps (100G SerDes, backplane Ethernet): both via capacitance AND stub resonance are relevant. Backdrilling or blind vias are essentially mandatory. The resonant notch from a 40–60 mil stub starts to fall within the channel’s operating band.

Backdrilling — how it works and what it costs

Backdrilling is a post-lamination secondary drilling operation that removes the via stub from the underside of the board using a slightly larger drill bit (typically via drill + 0.1–0.15 mm). The fab drills from the back to a controlled depth, removing the plated stub barrel. This reduces both the stub’s capacitance (primary benefit at PCIe Gen4/5 and DDR5) and eliminates the resonant stub (additional benefit at 25G+ SerDes).

Residual stub after backdrilling: controlled-depth drilling has a tolerance of ±0.1 mm, leaving a residual stub of typically 4–8 mil. At 4 mil, the resonant frequency is approximately 356 GHz — irrelevant for any current interface. The residual stub’s capacitance contribution is also negligible at < 10 mil stub length.

Specifying backdrill diameter: fabs typically run via drill + 0.1–0.15 mm (sufficient to clear the ~25 µm plating per side = 50 µm diametric). Specify via drill + 0.15 mm minimum in your fab notes (or via drill + 0.2 mm for a conservative margin, but verify annular ring clearance on any layers the backdrill passes through before tightening pitch below 0.8 mm).

Cost: backdrilling adds ~20–40% to bare-board cost for heavily backdrilled designs. Not all fabs offer it as standard. Lead time adds 2–5 days. Justified above PCIe Gen4 on long channels, or whenever the channel loss budget runs out without it.

Blind and buried vias — the alternative

A blind via connects an outer layer to one or more inner layers without drilling through the full board. Because it terminates where the signal exits, it has no stub — and its capacitance is lower than a PTH via because fewer layer pads contribute. The tradeoff is fabrication cost: sequential lamination adds 1–2 lamination cycles, typically doubling the fab cost per cycle, plus 1–2 weeks per cycle.

For pitch-constrained BGAs below 0.5 mm, blind microvias are necessary regardless of SI. For a standard 0.8–1.0 mm pitch BGA on an 8–12 layer board, backdrilling is almost always cheaper than converting to a blind-via stackup purely to reduce stub capacitance.

Decision framework

1. Calculate stub length: for each PTH via on high-speed nets, stub = board thickness − (exit layer depth + entry pad thickness).
2. Identify the primary concern: at < 25 Gbps, it’s via capacitance; at ≥ 25 Gbps, it’s both capacitance and resonance. Use a via capacitance calculator (or IBIS-AMI / full-wave EM tool for tight channels) to estimate the via discontinuity’s impact on your channel’s insertion-loss budget.
3. Check if the budget survives: if the channel total (trace length + connector + vias) fits within spec, you’re done. If not, backdrilling or via optimization is needed.
4. Choose the mitigation: backdrilling for existing PTH stackups; blind vias for HDI-constrained designs; via geometry optimization (smaller pad, larger antipad) as a first step before committing to backdrilling.
5. Document in fab notes: backdrill diameter (via drill + 0.15 mm minimum), depth from which side, which layers are backdrilled, and “remove anti-pads on backdrilled layers.”

The most common via-stub mistake isn’t forgetting to backdrill — it’s attributing PCIe Gen5 via problems to stub resonance when the actual mechanism is capacitive loading. Understanding which effect dominates tells you how much the via geometry matters vs. the stub removal.

Related

Signal integrity primer · DDR5 routing · PCIe Gen 5 layout · BGA escape routing · Stackup plane integrity