Signal integrity for PCB designers — a practical primer.

What signal integrity actually is

A digital signal is, at its physical core, a voltage waveform that transitions between two states. At low frequencies (< a few MHz), the waveform is nearly ideal — fast edges, clean logic levels, wide margins. As the edge rate increases (not just the frequency, but how fast each transition is), the PCB trace stops behaving like a wire and starts behaving like a transmission line. It has distributed capacitance and inductance; it can reflect; it can radiate; it can couple energy into neighboring conductors.

Signal integrity is the engineering discipline that ensures the waveform at the receiver still meets the device’s setup and hold time requirements, voltage thresholds, and noise margins — despite everything the board does to it. A clean signal is not an accident. It is the result of a stackup that controls impedance, a layout that manages return currents, and a floorplan that avoids unnecessary coupling.

The dividing line where SI thinking becomes necessary is roughly: any signal with edges faster than ~1 ns (rise time, not clock period). At 1 ns rise time, a 6-inch trace is comparable in length to the wavelength of the signal’s harmonics. Below that threshold, you can mostly ignore SI. Above it, you can’t.

Reflections and impedance

When a signal travels down a transmission line and encounters a change in characteristic impedance — a connector, a via, a change in trace width, the end of the trace — some energy reflects back toward the source. The reflection coefficient is:

A 50-Ω trace driving into an unterminated end (Z_L = ∞) reflects 100% of the incident wave, which means the incident and reflected signals add, doubling the voltage at the endpoint — and then that doubled waveform re-reflects back toward the source, bouncing back and forth until resistive loss damps it out. On a fast interface this creates ringing on the signal — the characteristic staircase pattern on a TDR plot.

The fix: match impedances. A controlled-impedance trace (50 Ω by convention for most single-ended signals, 100 Ω for differential) connected to a source with a matched output impedance and a terminated load minimizes reflections. Use the impedance calculator to find the trace geometry that hits your target for a given dielectric height and Dk.

Vias are a common hidden reflection source. A plated through-hole via has a parasitic capacitance from the pad/barrel geometry and inductance from the barrel, which together create an impedance discontinuity. At low frequencies it’s irrelevant. At PCIe Gen5 (16 GHz Nyquist) a single 0.3 mm via is a meaningful discontinuity — and the unused stub below the exit layer resonates like a shorted stub. See the via stubs and backdrilling article for the details.

Crosstalk

Every trace on a PCB is an antenna. When current flows through a trace, it creates a magnetic field that induces a voltage in adjacent traces (inductive coupling) and an electric field that capacitively couples charge to adjacent conductors (capacitive coupling). Together these are called crosstalk.

The aggressor drives the noise; the victim receives it. On the victim, crosstalk manifests in two places:

• Near-end crosstalk (NEXT): noise at the same end of the victim as the aggressor’s driver. NEXT is the worse of the two for most digital signals.
• Far-end crosstalk (FEXT): noise at the opposite end of the victim. On microstrip, FEXT is nonzero (the inductive and capacitive coupling coefficients do not fully cancel), but NEXT still dominates for most digital PCB geometries and rise times. On stripline, the two coupling terms nearly cancel, making FEXT very small — which is why high-speed traces are preferentially routed on stripline layers.

Crosstalk magnitude depends on: (a) the coupling coefficient between the traces (driven by proximity and dielectric height — tighter traces or thinner dielectrics increase coupling), (b) the coupled length, and (c) the signal rise time. The “3W rule” (keep trace center-to-center spacing ≥ 3 times the trace width) reduces coupling between adjacent traces to a level where NEXT is typically < 3% — adequate for most digital signals.

The fix: spacing, reference planes, and topology choice. Keep aggressor-victim spacing ≥ 3W for the length over which they run parallel. Route high-speed signals on stripline layers (sandwiched between two reference planes) where FEXT cancellation is better than microstrip. Never run a high-speed aggressor parallel to a high-speed victim for more than 1 inch without a guard trace or a reference-plane change.

Ground bounce and power noise

When a digital gate switches, the supply current it draws changes instantaneously. That current flows through the inductance of the power distribution network (PDN): the via to the plane, the lead bond or bump, the on-package routing. Inductance opposes instantaneous current change: V = L × dI/dt. The result is a transient perturbation on the supply and ground rails — ground bounce on the ground side, power droop on the supply side.

Ground bounce appears as a common-mode noise event on every output of the switching gate simultaneously. When multiple gates switch together (as in a data bus), the bounce adds. The receiving device sees a signal that shifts relative to its reference by the bounce voltage — this reduces noise margin and can cause false triggers.

The fix: decoupling capacitors and PDN design. The PDN’s job is to supply instantaneous current from the nearest possible source. Decoupling capacitors placed at the IC pins provide local charge reservoirs that limit the dI/dt seen by the bulk supply inductance. The PDN target impedance article explains how to size the decoupling network correctly. The Φ Z-PDN tool lets you visualize the impedance vs frequency.

Loss and eye closure

As signal frequency increases, two loss mechanisms increasingly attenuate the signal in a PCB trace:

• Conductor loss (skin effect): at high frequencies, current concentrates on the conductor surface within a “skin depth” (δ ∝ 1/√f). Less cross-sectional area = higher resistance. Conductor loss increases as √f.
• Dielectric loss: the dielectric (FR-4, Megtron 6, etc.) has a loss tangent (Df) that represents energy absorbed as heat when the electric field alternates. Dielectric loss increases linearly with frequency.

At 1 GHz on FR-4, these losses are modest. At 10+ GHz they become significant and eventually close the eye diagram: the overlay of all bit transitions, which looks like an “eye” when the signal is clean. As loss increases, the eye height and width shrink. When the eye closes, the receiver can no longer reliably distinguish 0 from 1 — bit errors result.

The fix is a combination of: shorter traces, lower-loss laminates, equalizers in the receiver, and proper via design. DDR5 and PCIe Gen5 systems run channels right up against the loss budget; DDR4 and PCIe Gen3 have margin. See the DDR5 routing guide for the loss-budget calculation methodology.

EMI — when SI escapes the board

SI and EMI are two faces of the same physics. When a signal has a fast edge, it radiates. The board is the antenna; the return current path determines the loop area; the loop area determines the radiation efficiency. Every SI problem is a potential EMI problem, and every EMI problem has an SI root cause.

The most common EMI source on digital boards is the return current path. A signal trace has an associated return current that flows, at high frequencies, directly under the signal trace in the reference plane. If the reference plane has a slot, a gap, or a split, the return current must detour — creating a large current loop that radiates. FCC and CISPR emissions tests catch this — but the fix is always a layout fix, never a filter fix after the fact.

See the EMC for power supplies article for the loop-by-loop breakdown on switching circuits specifically.

The five layout habits that prevent 90% of SI problems

1. Every high-speed signal has a continuous reference plane directly beneath it. No splits, no gaps, no slots under a high-speed trace. This single rule prevents more SI and EMI failures than all other rules combined. See the stackup plane integrity article for the mechanics.
2. Stitch every layer transition with a return via within 40 mil. When a signal changes layers, its return current must also change layers. Give it a low-inductance path (a ground via) nearby or the return current detours, creating a loop antenna.
3. Route differential pairs together, tight, and matched. Differential signaling (DDR DQS, PCIe TX/RX, USB) works because equal-and-opposite signals cancel common-mode noise. That cancellation only works if the pair is tightly coupled — same layer, tight spacing, matched length within ~1 ps intra-pair skew.
4. Decouple at the pin, not near the pin. A decoupling capacitor 10 mm from the IC has 10+ nH of inductance in series with it at GHz frequencies — worthless. Place the smallest, fastest decoupling caps (1–100 nF) directly against the power and ground pins of every high-speed device.
5. Control impedance by design, not by hope. Calculate the trace geometry for your target Z₀ before routing. Specify it on the fab drawing with a tolerance (±10% for most digital; ±5% for RF/mmWave). The fab will measure and adjust; if you don’t specify, they won’t.

You can run a board at DDR4-3200 or PCIe Gen3 without a simulator if you follow these five habits rigorously. Simulators become necessary when margins are tight (DDR5-6400+, PCIe Gen5), when channels are long, or when you need to prove you’re within spec for certification. The habits make the simulation tell you you’re fine.

Tools and articles to go deeper

Impedance calculator · Φ Z-PDN visualizer · DDR4 routing guide · Stackup plane integrity · Via stubs and backdrilling · PDN target impedance